Wafer-level chip scale package and method for fabricating and using the same

Abstract

A packaged semiconductor device (a wafer-level chip scale package) containing a conductive adhesive material as an electrical interconnect route between the semiconductor die and a patterned conductive substrate is described. The patterned conductive substrate acts not only as a substrate, but also as a redistribution layer that converts the dense pad layout of the die to a larger array configuration of the solder balls in the circuit board. Using the invention allows the formation of a lower priced chip scale package that also overcomes the restriction of the die size used in die-sized chip packages and the input-output pattern that can be required by the printed circuit board. Thus, the invention can provide a familiar pitch (i.e.,interface) to the printed circuit board for any small die.

1 . A wafer-level chip scale package, comprising: 
 a chip containing a stud bump;    a conductive substrate; and    an adhesive material containing conductive particles located between the chip and the substrate.    
     
     
         2 . The package of  claim 1 , wherein a conductive particle is located between the stud bump and the substrate.  
     
     
         3 . The package of  claim 1 , wherein the conductive particles comprise metal with an insulating layer.  
     
     
         4 . The package of  claim 1 , wherein the adhesive material comprises an anisotropic conductive film, an anisotropic conductive paste, or an isotropic conductive paste.  
     
     
         5 . The package of  claim 1 , wherein the chip contains an integrated circuit in communication with a chip pad.  
     
     
         6 . The package of  claim 1 , wherein the conductive substrate has been patterned.  
     
     
         7 . The package of  claim 6 , wherein the patterned conductive substrate serves as a redistribution layer.  
     
     
         8 . The package of  claim 1 , wherein the conductive substrate comprises copper.  
     
     
         9 . The package of  claim 8 , wherein the conductive substrate comprises copper foil.  
     
     
         10 . The package of  claim 1 , wherein the stud bump comprises Cu.  
     
     
         11 . A wafer-level chip scale package, comprising: 
 a chip containing a stud bump;    a conductive substrate; and    an adhesive material containing conductive particles located between the chip and the substrate with at least one conductive particle located between the stud bump and the bond pad.    
     
     
         12 . The package of  claim 11 , wherein the adhesive material comprises an anisotropic conductive film, an anisotropic conductive paste, or an isotropic conductive paste.  
     
     
         13 . The package of  claim 11 , wherein the conductive substrate has been patterned and the patterned conductive substrate serves as a redistribution layer.  
     
     
         14 . The package of  claim 11 , wherein the conductive substrate comprises copper foil.  
     
     
         15 . A packaged semiconductor device, comprising: 
 a chip containing a stud bump;    a patterned conductive substrate; and    an adhesive material containing conductive particles located between the chip and the substrate with at least one conductive particle located between the stud bump and the bond pad.    
     
     
         16 . The device of  claim 15 , wherein the adhesive material comprises an anisotropic conductive film, an anisotropic conductive paste, or an isotropic conductive paste.  
     
     
         17 . The device of  claim 15 , wherein the conductive substrate comprises copper foil.  
     
     
         18 . The package of  claim 15 , wherein the patterned conductive substrate serves as a redistribution layer.  
     
     
         19 . An electronic apparatus containing a packaged semiconductor device, the device comprising: 
 a chip containing a stud bump;    a conductive substrate; and    an adhesive material containing conductive particles located between the chip and the substrate.    
     
     
         20 . A method for making wafer-level chip scale package, comprising: 
 providing a chip containing a stud bump;    providing a conductive substrate; and    attaching the chip to the substrate using an adhesive material containing conductive particles.    
     
     
         21 . The method of  claim 20 , wherein the adhesive material comprises an anisotropic conductive film, an anisotropic conductive paste, or an isotropic conductive paste.  
     
     
         22 . The method of  claim 20 , further comprising patterning the conductive substrate.  
     
     
         23 . The method of  claim 22 , wherein the patterned conductive substrate serves as a redistribution layer.  
     
     
         24 . A method for making wafer-level chip scale package, comprising: 
 providing a chip with a stud bump;    providing a conductive substrate;    providing an adhesive material containing conductive particles on the chip, the substrate, or both;    pressing the chip and the substrate together; and    curing the adhesive material.    
     
     
         25 . The method of  claim 24 , further comprising providing the chip with a chip pad.  
     
     
         26 . The method of  claim 24 , including providing at least one conductive particle between the stud bump and the conductive substrate.  
     
     
         27 . The method of  claim 24 , wherein the adhesive material comprises an anisotropic conductive film, an anisotropic conductive paste, or an isotropic conductive paste.  
     
     
         28 . The method of  claim 24 , wherein the curing the adhesive material electrically and mechanically connects the chip to the substrate.  
     
     
         29 . The method of  claim 24 , further comprising patterning the conductive substrate.  
     
     
         30 . The method of  claim 29 , wherein the patterned conductive substrate serves as a redistribution layer.  
     
     
         31 . The method of  claim 24 , wherein the stud bump comprises Cu.  
     
     
         32 . A method for making an electronic apparatus containing a wafer-level chip scale package, the method comprising: 
 providing a chip containing a stud bump, providing a conductive substrate, and attaching the chip to the substrate using an adhesive material containing conductive particles; and    mounting the wafer-level chip scale package on a circuit board.