Split-gate flash with source/drain multi-sharing

Abstract

A multi-bit split-gate (MSG) flash cell with multi-shared source/drain and making of the same are disclosed. The MSG is formed with N+1 stacked gates comprising floating gates and control gates, separated by N select gates, all sharing the same source/drain between a pair of bit lines. With the disclosed MSG, a multiplicity of N+1 bit programming can be accomplished bit by bit where the programmed bits are selected by word line, bit line and control gate. In the erase operation, erased bits are selected by word line, while in the read operation, operations similar to write operation are performed. Thus, it is disclosed here that a plurality of N+1 bits or cells, where N is any integer, can be formed between two bit lines and along the same word line.

1 . A multi-bit split-gate (MSG) flash cell comprising: 
 a semiconductor substrate having a surface region of first conductivity type;    a first drain region and a second drain region formed in said surface region;    a plurality of (N+1) stacked gates separated apart by N select gates (SGs) between said first drain region and said second drain region, where N is an y interger;    a first bit line contacting said first drain region;    a second bit line contacting said second drain region; and    a word line contacting said select gate.    
   
   
       2 . The MSG flash cell according to  claim 1 , wherein said first drain region and second drain region are of second conductivity type opposite from said first conductivity type.  
   
   
       3 . The MSG flash cell according to  claim 1 , wherein said stacked gates comprise a floating gate and a control gate.  
   
   
       4 . The MSG flash cell according to  claim 4 , wherein said control gate (CG) can be addressed with a different address as a transfer gate (TG).  
   
   
       5 . The MSG flash cell according to  claim 3 , wherein said floating gate comprises a first polysilicon layer separated from said surface region by a first dielectric layer.  
   
   
       6 . The MSG flash cell according to  claim 3  or  4 , wherein said CG and TG comprise a second polysilicon layer separated from said first polysilicon layer by a second dielectric layer.  
   
   
       7 . The MSG flash cell according to  claim 1 , wherein said first bit line and second bit line comprise a third polysilicon layer separated from said first polysilicon layer and second polysilicon layer by a third and a fourth dielectric layer.  
   
   
       8 . The MSG flash cell according to  claim 1 , wherein said word line comprises a fourth polysilicon layer separated from said first polysilicon layer and from second polysilicon layer by said third and said fourth dielectric layers, and from said first and second bit lines by a fifth dielectric layer.  
   
   
       9 . The MSG cell according to  claim 1 , wherein said word line comprises a fourth polysilicon layer separated from said third polysilicon layer by a fourth dielectric layer.  
   
   
       10 . The MSG flash cell according to  claim 1 , wherein said select gate is shared by adjacent said stacked gates;  
   
   
       11 . The MSG flash cell according to  claim 1 , wherein the access of said first floating gate transistor is through the turn-on of next adjacent said select gate and next adjacent said floating gate.  
   
   
       12 . The MSG flash cell according to  claim 1 , wherein said word line is oriented generally normal to said first bit line and said second bit line.  
   
   
       13 - 28 . Canceled.