Apparatus, methods, and computer program products for determining the coefficients of a function with decreased latency.

Abstract

The present invention provides apparatus, methods, and computer program products that can decrease the latency with which the coefficients of a function representative of signal are determined. Specifically, the apparatus, methods, and computer program products of the present invention, taking advantage of the independence of samples, updates each of the coefficients of the function as each sample is received. As such, when the final sample is received, the apparatus, methods, and computer program products of the present invention need only update each coefficient with the contribution of the last sample prior to outputting the coefficients. As such, the latency from the time the last sample is received and the availability of the coefficients is decreased. To further decrease the latency, in one embodiment, the apparatus, methods, and computer program products of the present invention prestore either all or a portion of the possible values of the contribution of a sample to each coefficient, such that. As such, when the sample is received, the apparatus, methods, and computer program products of the present invention evaluate the value of the sample and retrieve the appropriate value from the prestored values that corresponds to the coefficient, sample, and value of the sample, thereby decreasing the time required to determine the coefficients. The apparatus, methods, and computer program products of the present invention also allow individual or subsets of the coefficients to be observed and also allow individual or subsets of the coefficients to be determined in varying resolutions.

1 - 101 . (Cancelled)  
   
   
       102 . An on-chip interconnection system, comprising: 
 a single semiconductor integrated circuit (IC);    a plurality of uni-directional buses disposed in the IC;    a peripheral-bus (p-bus) included in the plurality of uni-directional buses and that uses a simple non-pipelined protocol and supports both synchronous and asynchronous slave peripherals;    a p-bus controller connected to the p-bus and constituting an only bus-master, and including a centralized address decoder for generating a dedicated peripheral select signal, and providing for a connection to synchronous and asynchronous slave peripherals, and further providing for an input/output (I/O) backplane that allows a processor to configure and control any of its slave peripherals; and    an m-bus included in the plurality of uni-directional buses, and for providing a direct memory access (DMA) connection from any said slave peripherals to a main memory and permits peripherals to transfer data directly without processor intervention.    
   
   
       103 . The on-chip interconnection system of  claim 102 , wherein, there are included no tri-stated-buses, and no bidirectional buses.  
   
   
       104 . The on-chip interconnection system of  claim 102 , wherein, each signal has only a single buffer driver.  
   
   
       105 . The on-chip interconnection system of  claim 102 , wherein, any broadcast signals are re-driven by simple buffers with no extra control logic.  
   
   
       106 . The on-chip interconnection system of  claim 102 , wherein, only a single load is presented for point-to-point signals.  
   
   
       107 . The on-chip interconnection system of  claim 102 , wherein, any included peripherals exchange only control and status information, and do not directly exchange data between themselves.  
   
   
       108 . The on-chip interconnection system of  claim 102 , wherein, any data to be exchanged between peer peripherals is communicated through main memory using either programmed input/output (I/O) and direct memory access (DMA) transfer cycles.  
   
   
       109 . The on-chip interconnection system of  claim 102 , wherein, an exclusive use of point-to-point and broadcast signaling provides for increased bus.utilization efficiency that result from an elimination of bus-direction turn-around cycles.  
   
   
       110 . The on-chip interconnection system of  claim 102 , wherein, the p-bus includes a protocol and signaling method that permit memory-mapped. AS 1 C-type. register control.  
   
   
       111 . The on-chip interconnection'system of  claim 102 , wherein, all signals are launched and captured on a rising edge of a bus clock signal.  
   
   
       112 . The on-chip interconnection system of  claim 102 , wherein, any connected peripherals are operated at a clock signal frequency that differs from one used by the p-bus controller by including a wait signal.  
   
   
       113 . The on-chip interconnection system of  claim 102 , wherein, the p-bus includes logic latches for lower power consumption.  
   
   
       114 . The on-chip interconnection system of  claim 102 , wherein, the m-bus connects a CPU and any DMA-capable peripherals to a main memory via a memory access controller (MAC).  
   
   
       115 . The on-chip interconnection system of  claim 102 , wherein, the m-bus includes the use of pipelined address and data, and further includes hidden bus arbitration.  
   
   
       116 . The on-chip interconnection system of  claim 114 , wherein, said MAC is the only slave on the m-bus bus, and all m-bus transfer cycles are initiated by said CPU and DMA-capable peripherals.  
   
   
       117 . The on-chip interconnection system of  claim 114 , wherein, the IC is an application specific integrated circuit (ASIC).