Method, structure and process flow to reduce line-line capacitance with low-K material

Abstract

An improved method, structure and process flow for reducing line-line capacitance using low dielectric constant (K) materials is provided. Embodiments in accordance with the present invention form structures for semiconductor devices having a single level of interconnection as well as semiconductor devices having multiple levels of interconnection. In embodiments of the present invention, an initial dielectric structure is formed having a first low-K material overlaid with a standard-K material. In subsequent processing, conductive interconnects are formed and the standard-K material replaced with a second low-K material. In some embodiments of the present invention, the first and second low-K materials are the same material, in some embodiments the first and second low-K materials are different materials. Embodiments of the present invention having multiple levels of conductive interconnects are formed by employing methods and materials analogous to those used to form the first level of conductive interconnect and dielectric material disposed there between. Embodiments of the present invention employ low-K materials formed by spin-on processes as well as low-K materials formed by CVD processes.

1 - 40 . (Canceled).  
   
   
       41 . Integrated circuitry comprising: 
 a substrate;    a plurality of spaced blocks extending upward from the substrate, the spaced blocks comprising a first portion and a second portion over the first portion, the first portion comprising a low-K material and the second portion comprising sacrificial material, and the second portion comprising an upper surface of the spaced blocks; and    a conductive material disposed between the spaced blocks, the conductive material comprising an upper surface substantially coextensive with the upper surface of the spaced blocks.    
   
   
       42 . The circuitry of  claim 41  wherein the sacrificial material comprises a dielectric material other than a low-K material.  
   
   
       43 . The circuitry of  claim 41  wherein the sacrificial material comprises silicon oxide material.  
   
   
       44 . The circuitry of  claim 41  wherein the sacrificial material comprises oxide material.  
   
   
       45 . The circuitry of  claim 41  further comprising a barrier layer disposed between the first and second portions of the spaced blocks and disposed elevationally below the upper surface of the spaced blocks.  
   
   
       46 . The circuitry of  claim 41  further comprising a barrier layer disposed between the conductive material and the spaced blocks.  
   
   
       47 . The circuitry of  claim 41  wherein the sacrificial material comprises a material having a dielectric constant between that of silicon dioxide and silicon nitride.  
   
   
       48 . The circuitry of  claim 41  wherein the sacrificial material comprises a material having a dielectric constant greater than about 3.7 to 7.0.  
   
   
       49 . The circuitry of  claim 41  further comprising a barrier layer disposed between the first and second portions of the spaced blocks, the barrier layer comprising material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, nitrogen-comprising amorphous carbon, hydrogen-comprising amorphous carbon and silicon, and nitrogen-comprising amorphous carbon.  
   
   
       50 . The circuitry of  claim 41  wherein the sacrificial material comprises a thickness in the range of approximately 100 nm to approximately 1000 nm.