Chip mounting substrate, first level assembly, and second level assembly

Abstract

A chip mounting substrate comprising: a mounting base defined by a first surface and a second surface opposite to the first surface; a plurality of first lands disposed on the first surface, being classified into first and second groups of the first lands; and a plurality of second lands disposed on the second surface so as to face to the first lands, being classified into first and second groups of the second lands.

1 - 20 . (canceled)  
   
   
       21 . A semiconductor device, comprising: 
 a first mounting base defined by a first surface and second surface opposite to the first surface, the first surface having a first mounting area and a plurality of first lands, the second surface having a plurality of second lands opposite to the first lands, and each of the first lands are electrically connected to one of the second lands via a first through-hole, respectively;    a first semiconductor chip mounted on the first mounting area having a plurality of first pads electrically connected to the second lands, respectively;    a second mounting base mounted on the first mounting base having a same size as the first mounting base defined by a third surface and fourth surface opposite to the third surface, the third surface having a second mounting area and a plurality of third lands, the fourth surface having a plurality of fourth lands opposite to the third lands, each of third lands is electrically connected to one of the fourth lands via a second through-hole, respectively, each of fourth lands is electrically connected to one of the first lands via a first joint ball, respectively, and    a second semiconductor chip mounted on the second mounting area having a plurality of second pads electrically connected to the first lands via the fourth lands, respectively.    
   
   
       22 . The semiconductor device of  claim 21 , wherein a distance between the first surface and the fourth surface is longer than the distance between the first surface and an upper surface of the first semiconductor chip.  
   
   
       23 . The semiconductor device of  claim 21 , wherein the first and the second mounting base are BGA tapes.  
   
   
       24 . The semiconductor device of  claim 21 , wherein the first semiconductor chip is mounted in a face down configuration on the first chip mounting area.  
   
   
       25 . The semiconductor device of  claim 21 , further comprising: 
 a first heat sink contacted to the first semiconductor chip.    
   
   
       26 . The semiconductor device of  claim 21 , wherein the first lands are provided in the form of matrix over the remaining area of the first mounting area on the first surface.  
   
   
       27 . The semiconductor device of  claim 21 , wherein the first lands are aligned along a plurality of lines on one side of a square defining a periphery of the first mounting base.  
   
   
       28 . The semiconductor device of  claim 21 , wherein the first joint ball is made from solder.  
   
   
       29 . The semiconductor device of  claim 21 , further comprising: 
 a third mounting base mounted on the second mounting base having same size as the first mounting base defined by a fifth surface and sixth surface opposite to the fifth surface, the fifth surface having a third mounting area and a plurality of fifth lands, the sixth surface having a plurality of sixth lands opposite to the fifth lands, each of the fifth lands is electrically connected to one of the sixth lands via a third through-hole, respectively, each of sixth lands is electrically connected to the first lands via a second joint ball, respectively; and a third semiconductor chip mounted on the third mounting area.    
   
   
       30 . The semiconductor device of  claim 21 , further comprising: 
 a packaging board having a plurality of terminals; and    a plurality of packaging balls disposed on the terminals,    wherein the terminals are connected to the second lands via the packaging balls.    
   
   
       31 . The semiconductor device of  claim 21 , further comprising: 
 a packaging board having a substrate mounting area;    a plurality of connection terminals disposed on the substrate mounting area;    a plurality of signal terminals disposed around the substrate mounting area on the packaging board;    a plurality of signal wiring connected to the connection terminals and the signal terminals;    a plurality of packaging balls disposed on the connection terminals, respectively, wherein the second lands are connected to the connection terminals via the packaging balls.