Lead frame and semiconductor device using the same

Abstract

A lead frame has a die stage for mounting a semiconductor chip whose electrodes are electrically connected with leads via bonding wires, wherein they are enclosed in a molded resin, thus producing a semiconductor device. The outline of the die stage is shaped so as to be smaller than the outline of the semiconductor chip, and a plurality of cutouts are formed in the peripheral portion of the die stage so as to reduce the overall area of the die stage and to enhance the adhesion between the die stage and molded resin. The length L2 of each cutout ranges from (L1×0.05) to (L1×0.20) where L 1 denotes the length of each side of the die stage, and the overall area S2 of the die stage ranges from (S1×0.10) to (S1×0.40) where S1 denotes the overall area of the semiconductor chip.

1 . A lead frame comprising: 
 a die stage for mounting a semiconductor chip thereon, wherein an outline of the die stage is shaped to be smaller than an outline of the semiconductor chip; and    a plurality of cutouts formed in a peripheral portion of the die stage,    wherein the die stage and the semiconductor chip are integrally enclosed in a molded resin, which is introduced into the cutouts of the die stage.    
     
     
         2 . The lead frame according to  claim 1 , wherein the die stage has a rectangular shape, so that the plurality of cutouts are formed inwardly with respect to four sides of the die stage.  
     
     
         3 . The lead frame according to  claim 1 , wherein the cutouts are accompanied by half-etched portions formed inside of the die stage.  
     
     
         4 . The lead frame according to  claim 1 , wherein a plurality of secondary cutouts are formed inside of the die stage in relation to the cutouts.  
     
     
         5 . The lead frame according to  claim 1 , wherein a length L2 set for each of the cutouts is defined in a range from (L1×0.05) to (L1×0.20) where L1 denotes a length set for each side of the die stage.  
     
     
         6 . The lead frame according to  claim 1 , wherein an overall area S2 of the die stage is defined in a range from (S1×0.10) to (S1×0.40) where S1 denotes an overall area of the semiconductor chip.  
     
     
         7 . A semiconductor device comprising: 
 a semiconductor chip;    a lead frame having a die stage for mounting the semiconductor chip thereon, wherein an outline of the die stage is shaped so as to be smaller than an outline of the semiconductor chip;    a plurality of cutouts formed in a peripheral portion of the die stage; and    a molded resin for integrally enclosing the die stage and the semiconductor chip, wherein the molded resin is introduced into the cutouts of the die stage.    
     
     
         8 . The semiconductor device according to  claim 7 , wherein the die stage has a rectangular shape, so that the plurality of cutouts are formed inwardly with respect to four sides of the die stage.  
     
     
         9 . The semiconductor device according to  claim 7 , wherein the cutouts are accompanied by half-etched portions formed inside of the die stage.  
     
     
         10 . The semiconductor device according to  claim 7 , wherein a plurality of secondary cutouts are formed inside of the die stage in relation to the cutouts.  
     
     
         11 . The semiconductor device according to  claim 7 , wherein a length L2 set for each of the cutouts is defined in a range from (L1×0.05) to (L1×0.20) where L1 denotes a length set for each side of the die stage.  
     
     
         12 . The semiconductor device according to  claim 7 , wherein an overall area S2 of the die stage is defined in a range from (S1×0.10) to (S1×0.40) where S1 denotes an overall area of the semiconductor chip.  
     
     
         13 . The semiconductor device according to  claim 7 , wherein the lead frame is joined with a circuit board by use of non-lead solder.