Stencil mask and method of producing the same, semiconductor device produced using the stencil mask and method of producing the semiconductor device

Abstract

A stencil mask is disclosed which can be produced by performing pattern correction in a practically applicable comparatively short period of time. When stencil mask pattern data are corrected by a stress analysis, displacement amounts are calculated for those of stencil hole patterns which have a size equal to or greater than a predetermined size. As a result, stencil mask pattern data having corrected patterns are obtained in a comparatively short period of time which can be applied industrially. By producing a stencil mask based on the patterns, a stencil mask in which a desired pattern is formed is obtained.

1 - 4 . (Canceled)  
     
     
         5 . A stencil mask, comprising a stencil mask body on which a desired pattern shape is formed based on a pattern shape obtained by calculating displacement amounts arising from an opening of each of only those stencil hole patterns which have a size equal to or greater than a predetermined size for each of the stencil hole patterns and correcting the hole pattern based on results of the calculation.  
     
     
         6 . A stencil mask according to  claim 5 , wherein, in order to obtain the pattern shape, in addition to the calculation of the displacement amounts of only those the stencil hole patterns which have a size equal to or greater than the predetermined size, correction of the position displacement amounts of those of the stencil hole patterns which have a size smaller than the predetermined size is performed.  
     
     
         7 . A stencil mask according to  claim 6 , wherein, in order to obtain the pattern shape, in addition to the calculation of the displacement amounts of only those stencil hole patterns which have a size equal to or greater than the predetermined size, the calculation of the displacement amounts is performed by providing, for each of those stencil hole patterns which have a size smaller than the predetermined size, making use of a stress relationship represented by an expression {p}=At[B] T [D][B] {d} for the plane stress analysis, {p} being a vector of an external force applied to a node, A being the area of an element, t being the thickness of the element, [B] being a displacement-distortion matrix of the element, [B] T  being a transposed matrix of [B], [D] being a stress-distortion matrix of the element, and {d} being a displacement amount vector of the node, a variation in volume by the stencil hole pattern to At in the expression for each elements of the analysis without providing pattern shape information.  
     
     
         8 . A stencil mask according to  claim 5 , wherein each oblique lines and curved lines of a contour of the formed desired pattern shape is modified to a stepwise line of a correction pitch smaller than a pitch of an allowable value.  
     
     
         9 . A semiconductor device having a surface on which a pattern shape corresponding to a desired pattern on a stencil mask, on which the desired pattern shape is formed based on a pattern shape obtained by calculating displacement amounts arising from an opening of each of only those stencil hole patterns which have a size equal to or greater than a predetermined size for each of the stencil hole patterns and correcting the hole pattern based on results of the calculation, is formed by irradiating a charged particle beam upon the stencil mask so that the charged particle beam passing through the stencil mask may be irradiated upon the surface of said semiconductor device.  
     
     
         10 . A semiconductor device according to  claim 9 , wherein the pattern shape is formed using the stencil mask formed by performing, in addition to the calculation of the displacement amounts of only those stencil hole patterns which have a size equal to or greater than the predetermined size, correction of the position displacement amounts of those of the stencil hole patterns which have a size smaller than the predetermined size is performed.  
     
     
         11 . A semiconductor device according to  claim 10 , wherein the pattern shape is formed using the stencil mask formed by performing, in addition to the calculation of the displacement amounts of only those stencil hole patterns which have a size equal to or greater than the predetermined size, the calculation of the displacement amounts by providing, for each of those stencil hole patterns which have a size smaller than the predetermined size, making use of a stress relationship represented by an expression {p}=At[B] T [D][B] {d} for the plane stress analysis, {p} being a vector of an external force applied to a node, A being the area of an element, t being the thickness of the element, [B] being a displacement-distortion matrix of the element, [B] T  being a transposed matrix of [B], [D] being a stress-distortion matrix of the element, and {d} being a displacement amount vector of the node, a variation in volume by the stencil hole pattern to At in the expression for each elements of the analysis without providing pattern shape information.  
     
     
         12 . A semiconductor device according to  claim 9 , wherein the pattern shape is formed using the stencil mask wherein each oblique lines and curved lines of a contour of the formed desired pattern shape is modified to a stepwise line of a correction pitch smaller than a pitch of an allowable value.  
     
     
         13 - 16  (Canceled)