Pixel circuit with shared active regions

Abstract

An LCD pixel device is provided of the type deployed in a matrix of pixels selectively energized by a plurality of row lines and plurality of column lines and wherein a video voltage is stored on at least one pixel capacitor and coupled to an image-generating device. First and second source regions are formed near the surface of a semiconductor substrate. A drain region is likewise formed in the substrate between the first and second source regions forming the channels of first and second field-effect-transistors. An insulating layer is formed on the substrate, and first and second gate electrodes are provided in the insulating layer between the first source region and the drain region and the second source region and the drain region respectively. First and second mirrors are provided on the surface of the insulating layer. Conductive interconnects formed in the insulating layer provide electrical coupling between the first and second transistors, the first and second capacitors, and the first and second mirrors, respectively.

1 - 25 . (canceled)  
     
     
         26 . A method, in a liquid crystal display (LCD), for providing a matrix of pixels selectively energized by a plurality of row lines and a plurality of column lines and wherein a video voltage is stored on at least one pixel capacitor coupled to an image-generating device, said method comprising the steps of: 
 providing a substrate having a first surface;    forming first and second source regions on the substrate proximate to the first surface;    forming a drain region on the substrate proximate to the first surface and between the first and second source regions;    forming a first channel of a first field-effect-transistor between the first source region and the drain region;    forming a second channel of a second field-effect-transistor between the second source region and the drain region;    forming an insulating layer having a second surface on the first surface;    forming first and second gate electrodes in the insulating layer proximate the first channel and the second channel, respectively, and coupled to first and second ones, respectively, of a plurality of row lines;    forming a drain electrode in the insulating layer;    coupling the drain electrode to one of a plurality of column lines;    forming first and second capacitors in the insulating layer;    forming first and second mirrors on the second surface; and    forming first and second interconnects in the insulating layer for providing electrical coupling between the first source region, the first capacitor, and the first mirror, and between the second source region, the second capacitor, and the second mirror, respectively.    
     
     
         27 . The method according to  claim 26 , wherein the substrate is a p-doped silicon substrate.  
     
     
         28 . The method according to  claim 27 , wherein the first and second source regions are n-doped silicon.  
     
     
         29 . The method according to  claim 28  wherein the drain region is n-doped silicon.  
     
     
         30 . The method according to  claim 29 , wherein the insulating layer is silicon dioxide.  
     
     
         31 . The method according to  claim 30 , wherein the first and second capacitors are polysilicon capacitors.  
     
     
         32 . The method according to  claim 31  wherein the first and second mirrors are aluminum.  
     
     
         33 . The method according to  claim 32  wherein the first and second interconnects are aluminum.  
     
     
         34 . The method according to  claim 26 , further comprising the step of deploying first and second guard rings around the first and second interconnects, respectively.  
     
     
         35 . A method, in a liquid crystal display (LCD), for generating an image from a video signal, the LCD having a matrix of pixels arranged in a plurality of rows and a plurality of columns which are selectively energized to create the image of the video signal, said method comprising the steps of: 
 providing at least first and second row lines;    providing at least one column line;    providing a substrate having a first surface;    forming first and second source regions in the substrate proximate to the first surface;    forming a drain region in the substrate proximate to the first surface and between the first and second source regions;    forming a first channel of a first field-effect-transistor between the first source region and the drain region;    forming a second channel of a second field-effect-transistor between the second source region and drain region;    forming an insulating layer on the first surface;    forming first and second gate electrodes in said insulating layer proximate to the first channel and said second channel, respectively, and coupled to the at least first and second row lines, respectively;    forming a drain electrode in the insulating layer;    coupling the drain electrode to the at least one column line;    forming first and second capacitors in the insulating layer;    forming first and second mirrors on the second surface; and    forming first and second interconnects in the insulating layer for providing electrical coupling between the first source region, the first capacitor, the said first mirror, and between the second source region, the second capacitor, and the second mirror, respectively.    
     
     
         36 . The method according to  claim 35 , wherein the substrate is a p-doped silicon.  
     
     
         37 . The method according to  claim 36 , wherein the first and second source regions and the drain regions are a n-doped silicon.  
     
     
         38 . The method according to  claim 37 , wherein the first and second capacitors are polysilicon capacitors.  
     
     
         39 . The method according to  claim 38 , wherein the first and second mirrors are aluminum.  
     
     
         40 . The method according to  claim 35  further comprising the step of deploying first and second guard rings around the first and second interconnects, respectively.