US2004262735A1PendingUtilityA1

Semiconductor device and production method thereof

Priority: Dec 16, 1999Filed: May 24, 2004Published: Dec 30, 2004
Est. expiryDec 16, 2019(expired)· nominal 20-yr term from priority
H05K 3/4602H05K 1/186H10W 90/732H10W 90/724H10W 90/00H10W 70/614H10W 70/093H10W 72/851
44
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Claims

Abstract

In a semiconductor device including an insulating core substrate, a plurality of layers of wiring patterns on the core substrate and insulating layers interposed between the wiring patterns, each adjacent pair of the wiring patterns being electrically connected through a conductor portion penetrating through the insulating layer interposed between them, each of the insulating layers is formed integrally, semiconductor chips thinner than one layer of the insulating layer are mounted into at least one of the insulating layers, and the semiconductor chips are electrically connected to one layer of the wiring pattern of one insulating layer adjacent on the side of the core substrate.

Claims

exact text as granted — not AI-modified
1 . (Cancelled)  
     
     
         2 . (Cancelled)  
     
     
         3 . (Cancelled)  
     
     
         4 . (Cancelled)  
     
     
         5 . (Cancelled)  
     
     
         6 . A method of producing a semiconductor device including an insulating core substrate, a plurality of layers of wiring pattern on said core substrate, and insulating layers each interposed between said wiring patterns, each adjacent pair of said wiring patterns being electrically connected to each other through conductor portions penetrating through said insulating layer interposed between said adjacent wiring patterns, said method comprising the steps of: 
 press-bonding one of the surfaces of an electric insulating film having a conductor layer formed on the other surface thereof to a surface of the core substrate, on which surface semiconductor chips electrically connected to said wiring pattern by flip-chip bonding are mounted, to form an electric insulating layer covering said semiconductor chips and said wiring patterns;  
 etching said conductor layer to form a wiring pattern on a surface of said electric insulating layer;  
 forming via-holes in said electric insulating layer to expose said wiring pattern of a lower layer as a bottom thereof;  
 forming a connection portion in each of said via-holes so as to electrically connect said wiring pattern of a lower layer and said wiring pattern formed in said electric insulating layer; and  
 mounting said semiconductor chips while being electrically connected by flip=chip bonding to said wiring pattern formed on the surface of said wiring pattern formed on the surface of said electric insulating layer.  
 
     
     
         7 . (Cancelled)

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