Extendible process for improved top oxide layer for DRAM array and the gate interconnects while providing self-aligned gate contacts

Abstract

A Top Oxide Method is used to form an oxide layer over an array of vertical transistors as in a trench dynamic random access memory (DRAM) array with vertically stacked access metal oxide semiconductor field effect transistors (MOSFETs). The Top Oxide is formed by first forming the vertical devices with the pad nitride remaining in place. Once the devices have been formed and the gate polysilicon has been planarized down to the surface of the pad nitride, the pad nitride is stripped away leaving the tops of the gate polysilicon plugs extending above the active silicon surface. This pattern of polysilicon plugs defines the pattern over which the Top Oxide is deposited. The deposited Top Oxide fills the regions between and on top of the polysilicon plugs. The Top Oxide is then planarized back to the tops of the polysilicon plugs so contacts can be made between the passing interconnects and the gates of the vertical devices. The Top Oxide layer serves to separate the passing interconnects from the active silicon thereby reducing capacitive coupling between the two levels and providing a robust etch-stop layer for the reactive ion etch (RIE) patterning of the subsequent interconnect level.

1 . A semiconductor structure comprising: 
 a vertical metal oxide semiconductor field effect transistor (MOSFET) array formed in a silicon substrate;    a wiring layer that interconnects gates of vertical MOSFETs of the MOSFET array; and    an oxide layer disposed between the MOSFET array and the wiring layer;    the gate conductors of the vertical MOSFETs extending vertically through the oxide and having a constant cross-sectional dimension.    
     
     
         2 . The semiconductor structure of  claim 1 , further comprising isolation trenches filled with insulating material that electrically insulates the vertical MOSFETs from one another.  
     
     
         3 . The semiconductor structure of  claim 1 , wherein a thickness of the oxide layer is adjustable over a wide range.  
     
     
         4 . The semiconductor structure of  claim 1 , wherein a top surface of the oxide is coplanar with top surfaces of gate polysilicon extensions of the MOSFETs and is parallel to a surface of the silicon substrate.  
     
     
         5 . The semiconductor structure of  claim 1 , wherein a thickness of the oxide is approximately equal over the MOSFET array and over portions of the substrate beyond the MOSFET array.  
     
     
         6 . The semiconductor structure of  claim 1 , wherein the oxide layer is present only over predefined regions of the silicon substrate, said predefined regions including a region of the MOSFET array.