Configurable decoder

Abstract

Briefly, a configurable decoder to decode signals of communication systems is provided. The configurable decoder may include a programmable metric data generator to reconfigure an add-compare-select unit according to a predetermined data structure provided by a desired communication protocol and a programmable traceback unit to provide decoded data according to the desired communication protocol.

What is claimed is:  
     
         1 . An apparatus comprises: 
 a programmable metric data generator to reconfigure an add-compare-select unit according to a predetermined data structure provided by a desired communication protocol; and    a programmable traceback unit to provide decoded data according to the desired communication protocol.    
     
     
         2 . The apparatus of  claim 1 , wherein the programmable metric data generator comprise a first programmable logic device to be programmed using a hardware description language and the programmable traceback unit comprises a second programmable logic device to be programmed using the hardware description language.  
     
     
         3 . The apparatus of  claim 1  wherein the programmable metric generator is able to compute a branch metric based on the probability of a received symbol being substantially equal to a branch symbol.  
     
     
         4 . The apparatus of  claim 1 , wherein the programmable metric generator is able to compute a squared Euclidean distance or Hamming distance between a received symbol and a branch symbol.  
     
     
         5 . The apparatus of  claim 1 , wherein the programmable metric generator further comprises at least one of a path metric data generator and a branch metric generator.  
     
     
         6 . The apparatus of  claim 5 , wherein the path metric data generator comprises: 
 a path metric state machine to read and to shuffle the path metrics values.    
     
     
         7 . The apparatus of  claim 5 , wherein the path metric data generator comprises 
 a path metric memory unit to store a plurality of path metrics and the path metric state machine.    
     
     
         8 . The apparatus of  claim 5 , wherein the path metric state machine comprises: 
 a plurality of address generators to select a predetermined number of previously generated path metrics stored in the path metric memory unit;    a shuffler to route the path metrics to the add-compare-select unit; and    a multiplexer to select the path metrics to be input to the add-compare-select unit.    
     
     
         9 . The apparatus of  claim 8 , wherein the shuffler and the multiplexer are implemented in a programmable logic and are able to be programmed according to the desired communication protocol.  
     
     
         10 . The apparatus of  claim 5 , wherein the branch metric generator comprises: 
 a branch metric state machine to read branch metric values from the branch metric memory unit and to distribute the branch metric values to the add-compare-select unit.    
     
     
         11 . The apparatus of  claim 5 , wherein the branch metric generator comprises: 
 a branch metric memory unit to store a plurality of a newly generated branch metrics.    
     
     
         12 . The apparatus of  claim 10 , wherein the branch metric state machine comprises a programmable logic device able to be programmed according to the desired communication protocol.  
     
     
         13 . The apparatus of  claim 1 , wherein the add-compare-select unit comprises a predetermined number of add-compare select units.  
     
     
         14 . The apparatus of  claim 1 , wherein the programmable traceback unit is able to store winning branch decisions.  
     
     
         15 . The apparatus of  claim 1 , wherein the programmable traceback unit is able to reconstruct a state sequence and to reconstruct a decoded bit sequence.  
     
     
         16 . The apparatus of  claim 1 , wherein the programmable traceback unit comprises: 
 a traceback state machine to receive a bit read from the cache memory and to output a read address and decoded bits.    
     
     
         17 . The apparatus of  claim 1 , wherein the programmable traceback unit comprises: 
 a cache memory to store a selected branch of the branch metric and the traceback state machine.    
     
     
         18 . The apparatus of  claim 16 , wherein the traceback state machine comprises a traceback read address generator.  
     
     
         19 . The apparatus of  claim 16 , wherein the traceback state machine is implemented by a random accessed memory based programmable logic device to be programmed by downloading a circuit description of the traceback state machine.  
     
     
         20 . The apparatus of  claim 1  is configured to decode a received signal.  
     
     
         21 . An apparatus comprising: 
 a dipole antenna to receive a signal; and    a configurable decoder to decode the received signal, the decoder comprising a programmable metric data generator to reconfigure an add-compare-select unit according to data structure of the received signal.    
     
     
         22 . The apparatus of  claim 21 , wherein the configurable decoder further comprises: 
 a programmable traceback unit; and    the programmable metric data generator comprise a first programmable logic device to be programmed using a hardware description language and the programmable traceback unit comprises a second programmable logic device to be programmed using the hardware description language.    
     
     
         23 . The apparatus of  claim 21 , wherein the programmable metric generator is able to compute Hamming distance between a received symbol and a branch symbol.  
     
     
         24 . The apparatus of  claim 21 , wherein the programmable metric generator further comprises a path metric data generator and a branch metric data generator.  
     
     
         25 . The apparatus of  claim 24 , wherein the path metric data generator comprises: 
 a path metric memory unit to store a plurality of path metrics; and    a path metric state machine to read and to shuffle the path metrics values.    
     
     
         26 . The apparatus of  claim 25 , wherein the path metric state machine comprises: 
 a plurality of address generators to select a predetermined number of previously generated path metrics stored in the path metric memory unit;    a shuffler to route the appropriate path metrics to the add-compare-select unit; and    a multiplexer to select the path metrics to be input to the add-compare-select unit.    
     
     
         27 . The apparatus of  claim 26 , wherein the shuffler and the multiplexer are implemented in programmable logic and are able to be programmed according to the desired communication protocol.  
     
     
         28 . The apparatus of  claim 25 , wherein the branch metric generator comprises: 
 a branch metric memory to store a plurality of newly generated branch metrics; and    a branch metric state machine to read branch metric values from the branch metric memory and to distribute the branch metric values to the add-compare-select unit.    
     
     
         29 . The apparatus of  claim 28 , wherein the branch metric state machine comprises a programmable logic device and is able to be programmed according to a desired communication protocol.  
     
     
         30 . The apparatus of  claim 21 , wherein the add-compare-select unit comprises a predetermined number of add-compare select units.  
     
     
         31 . The apparatus of  claim 21 , further comprising a programmable traceback unit to store winning branch decisions.  
     
     
         32 . The apparatus of  claim 21 , wherein the programmable traceback unit is able to reconstruct a state and to reconstruct a decoded bit sequence.  
     
     
         33 . The apparatus of  claim 21 , wherein the programmable traceback unit comprises: 
 a cache memory to store two or more selected branches of the branch metric; and    a traceback state machine to receive two or more bits read from the cache memory and to output a read address and two or more decoded bits.    
     
     
         34 . The apparatus of  claim 33 , wherein the traceback state machine comprises a traceback read address generator.  
     
     
         35 . The apparatus of  claim 33 , wherein the traceback state machine is implemented by a random access memory based programmable logic device to be programmed by downloading a circuit description of the traceback state machine.  
     
     
         36 . The apparatus of  claim 21  is configured to decode a received signal.  
     
     
         37 . A method comprising: 
 reconfiguring a decoder by downloading a circuit description of a state machine of the decoder,    wherein the circuit description is able to program the state machine of the decoder.    
     
     
         38 . The method of  claim 37 , wherein the state machine comprises at least one of a state machine of a path metric generator and a state machine of a branch metric generator and wherein reconfiguring comprises: 
 reconfiguring at least one of the state machine of the path metric and the state machine of the branch metric generator.    
     
     
         39 . The method of  claim 37 , wherein the state machine comprises a state machine of a traceback unit and wherein reconfiguring comprises: 
 reconfiguring the state machines of the traceback unit.    
     
     
         40 . A communication system comprises: 
 a transmitter to transmit an encoded signal; and    a receiver comprising a reconfigurable decoder able to be reconfigured to decode the encoded signal by downloading a circuit description to reconfigure the circuit of the decoder.    
     
     
         41 . The communication system of  claim 40 , wherein the reconfigurable decoder comprises: 
 a programmable metric data generator to reconfigure data routing to an add-compare-select unit according to data structure of the encoded signal provided by a desired communication protocol.    
     
     
         42 . The communication system of  claim 41 , wherein the programmable metric data generator further comprises a path metric data generator and a branch metric data generator.  
     
     
         43 . The communication system of  claim 42 , wherein the path metric state machine comprises: 
 a plurality of address generators to select a predetermined number of previous generated path metrics stored in the path metric memory;    a shuffler to route at least some of the path metrics to the add-compare-select unit; and    a multiplexer to select from at least some path metrics the path metrics to be input to the add-compare-select unit.    
     
     
         44 . The communication system of  claim 43 , wherein the shuffler and the multiplexer are both implemented in a programmable logic able to be programmed according to the desired communication protocol.  
     
     
         45 . The communication system of  claim 43 , wherein the branch metric generator comprises: 
 a branch metric memory to store a plurality of newly generated branch metrics; and    a branch metric state machine to read branch metric values from the branch metric memory and to distribute the branch metric values to the add-compare-select unit.    
     
     
         46 . The communication system of  claim 45 , wherein the branch metric state machine comprises programmable logic able to be programmed according to the desired communication protocol.  
     
     
         47 . The communication system of  claim 40 , wherein the reconfigurable decoder comprises a programmable traceback unit.  
     
     
         48 . The communication system of  claim 47 , wherein the programmable traceback unit comprises: 
 a cache memory to store two or more selected branches of the branch metric; and    a traceback state machine to receive two or more bits read from the cache memory and to output a read address and two or more decoded bits.    
     
     
         49 . The communication system of  claim 47 , wherein the traceback state machine is implemented by a random access memory based programmable logic device to be programmed by downloading a circuit description of the traceback state machine.