US2004255197A1PendingUtilityA1

Multi-staged bios-based memory testing

44
Priority: Dec 21, 2000Filed: Jul 13, 2004Published: Dec 16, 2004
Est. expiryDec 21, 2020(expired)· nominal 20-yr term from priority
Inventors:Todd Schelling
G06F 11/2284
44
PatentIndex Score
0
Cited by
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References
0
Claims

Abstract

The BIOS of a multiple processor system passes partial control to the operating system following an abbreviated power-on initialization. The BIOS program retains control of one or more processors and any memory that was untested during power-on. While the operating system is loaded and the system is operational, the BIOS program tests the retained memory. The BIOS program then relinquishes control of the retained memory and processor(s) during runtime to the operating system.

Claims

exact text as granted — not AI-modified
1 . A method comprising: 
 passing control of at least one portion of a processor-based system to an operating system loaded on the processor-based system; and    retaining control of a second portion of the processor-based system by a power-on program.    
     
     
         2 . The method of  claim 1 , further comprising: 
 running both the power-on program and the operating system program simultaneously.    
     
     
         3 . A method comprising: 
 passing control of at least one portion of a processor-based system to an operating system loaded on the processor-based system; and    retaining control of a second-portion of the processor-based system by a power-on program,    retaining control of a second portion of the processor-based system further compromising retaining control of at least one processor of a plurality of processors.    
     
     
         4 . The method of  claim 2 , further comprising: 
 retaining a portion of a memory by the power-on program; and performing memory operations on the retained portion of the memory by the power-on program while the operating system is running.    
     
     
         5 . A method comprising: 
 passing control of at least one portion of a processor-based system to an operating system loaded on the processor-based system;    retaining control of a second portion of the processor-based system by a power-on program;    running both the power-on program and the operating system program simultaneously;    retaining a portion of a memory by the power-on program; performing memory operations on the retained portion of the memory by the power-on program while the operating system is running;    relinquishing a second portion of the memory to the operating system; and    performing memory operations on the relinquished portion of the memory by the operating system while the power-on program is running.    
     
     
         6 . A method comprising: 
 passing control of at least one portion of a processor-based system to an operating system loaded on the processor-based system;    retaining control of a second portion of the processor-based system by a power-on program;    running both the power-on program and the operating system program simultaneously;    retaining a portion of a memory by the power-on program;    performing memory operations on the retained portion of the memory by the power-on program while the operating system is running;    performing memory operations on the retained portion of the memory by the power-on program while the operating system is running further comprising:    initializing the retained portion of memory; and    testing the retained portion of memory.    
     
     
         7 . The method of  claim 3 , retaining control of at least one processor of a plurality of processors further comprising: 
 identifying the plurality of the processors available to the system in a table readable by the operating system;    notifying the operating system that the plurality of the processors are available; and    declining to include the at least one processor in the table.    
     
     
         8 . The method of  claim 7 , running both the power-on program and the operating system simultaneously further comprising: 
 executing the power-on program by the at least one processor of the plurality of processor; and    executing the operating system by a second processor, wherein the second processor is identified by the table.    
     
     
         9 . A system comprising: 
 a first storage to store a power-on program;    a second storage to store an operating system;    a first element controlled by the operating system; and    a second element controlled by the power-on program.    
     
     
         10 . The system of  claim 9 , wherein the first element is a first processor and the power-on program executes on the first processor.  
     
     
         11 . The system of  claim 10;  wherein the second element is a second processor and the operating system executes on the second processor.  
     
     
         12 . A system comprising: 
 a first storage to store a power-on program;    a second storage to store an operating system;    a first element controlled by the operating system;    a second element controlled by the power-on program,    wherein the first element is a first processor and the power-on program executes on the first processor,    wherein the second element is a second processor and the operating system executes on the second processor, and    a configuration table accessible to both the power-on routine and the operating system to identify the first element.    
     
     
         13 . The system of  claim 9 , wherein the first element is a first portion of a memory.  
     
     
         14 . The system of  claim 13 , wherein the second element is a second portion of the memory.  
     
     
         15 . An article comprising a medium storing instruction to enable a processor-based system to: 
 pass control of at least one portion of the processor-based system to an operating system loaded on the processor-based system;    retain control of a second portion of the processor based system by a power-on program; and    run both the power-on program and the operating system program simultaneously.    
     
     
         16 . The article of  claim 15 , further storing instructions to enable a processor-based system to: 
 retain a portion of a memory by the power-on program; and    perform memory operations on the retained portion of the memory by the power-on program while the operating system is running.    
     
     
         17 . An article comprising a medium storing instructions to enable a processor-based system to: 
 pass control of at least one portion of the processor-based system to an operating system loaded on the processor-based system;    retain control of a second portion of the processor-based system by a power-on program;    run both the power-on program and the operating system program simultaneously;    retain a portion of a memory by the power-on program;    perform memory operations on the retained portion of the memory by the power-on program while the operating system is running;    relinquish a second portion of the memory to the operating system; and    perform memory operations on the relinquished portion of the memory by the operating system while the power-on program is running.    
     
     
         18 . The article of  claim 17 , further storing instructions to enable a processor-based system to: 
 identify the plurality of processors available to the processor-based system in a table readable by the operating system;    notify the operating system that the plurality of processors are available; and    decline to include at least one processor of the plurality of processors in the table.    
     
     
         19 . The article of  claim 18 , further storing instructions to enable a processor-based system to: 
 execute the power-on program by the at least one processor of the plurality of processors; and    execute the operating systems by a second processor, wherein the second processor is identified in the table.    
     
     
         20 . A method comprising: 
 receiving control of a portion of a processor-based system by an operating system; and    receiving control of a second portion of the processor-based system while executing an operating system.    
     
     
         21 . The method of  claim 19 , receiving control of a second portion of the processor-based system while executing the operating system further comprising: 
 receiving an interrupt; and    receiving methods that describe the second portion.    
     
     
         22 . An article comprising a medium storing instructions to enable a processor-based system to: 
 receive control of a portion of the processor-based system by an operating system; and    receive control of a second portion of the processor-based system while executing an operating system.    
     
     
         23 . The article of  claim 22 , further storing instructions to enable a processor-based system to: 
 receive an interrupt; and    receive methods that describe the second portion    
     
     
         24 . A system comprising: 
 two or more processors;    a device comprising a first portion and a second portion, wherein the device is coupled to the two or more processors; and    a power-on routine executable by one of the two or more processors, wherein the power-on routine relinquishes control of the first portion of the device before loading an operating system.    
     
     
         25 . A system comprising: 
 two or more processors;    a device comprising a first portion and a second portion, wherein the device is coupled to the two or more processors; and    a power-on routine executable by one of the two or more processors, wherein the power-on routine relinquishes control of the first portion of the device before loading an operating system,    wherein the power-on routine further: 
 tests the second portion of the device while the operating system is running; and  
 relinquishes control of the second portion of the device to the operating system.  
   
     
     
         26 . The system of  claim 25 , wherein the device is a memory.  
     
     
         27 . The system of  claim 25 , wherein the device is a group of processors and the first portion of the device is a first processor and the second portion of the device is a second group of processors.  
     
     
         28 . A system comprising: 
 two or more processors;    a device comprising a first portion and a second portion, wherein the device is coupled to the two or more processors; and    an operating system executable by one of the two or more processors, wherein the operating system receives control of the first portion of the device when the operating system is executed.    
     
     
         29 . The system of  claim 28 , further comprising: 
 a power-on routine to relinquish control of the first portion of the device to the operating system.    
     
     
         30 . A system comprising: 
 two or more processors;    a device comprising a first portion and a second portion, wherein the device is coupled to the two or more processors;    an operating system executable by one of the two or more processors, wherein the operating system receives control of the first portion of the device when the operating system is executed; and    a power-on routine to relinquish control of the first portion of the device to the operating system,    wherein the operating system further: 
 receives an interrupt form the power-on routine; and  
   receives control of the second portion of the device.

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