Method and apparatus for control of another device through an ide bus

Abstract

A method and apparatus for an IDE device to control a second device through an IDE bus. The IDE device includes firmware, a microprocessor, and a plurality of registers. The IDE device can read specific registers in the second device by storing a value indicating the request in a register of the IDE device and issuing an Interrupt signal (INTRQ). An implementation circuit in the second device then makes the contents of the specific register available to be read by the IDE device and clears the INTRQ. Similarly, the IDE device can write to a specific register of the second device by storing the request and the data to be written into predetermined registers in the IDE device and issuing an INTRQ signal. The implementation circuit then causes the data to be written into the specific register of the second device indicated by the request and clears the INTRQ.

What is claimed is:  
     
         1 . A data storage device comprising: 
 a microprocessor for execution of computer code;    a memory comprising the computer code to be executed, the computer code capable of controlling a compatible device through an Integrated Device Electronics (IDE) bus, the IDE bus connecting the data storage device with the compatible device; and    a plurality of registers utilized by the computer code to control the compatible device.    
     
     
         2 . The data storage device of  claim 1  wherein the compatible device is a bridge, the bridge connected to a host computer system.  
     
     
         3 . The data storage device of  claim 2  wherein the bridge communicates with the host computer system utilizing a communication protocol incompatible with an IDE communications protocol.  
     
     
         4 . The data storage device of  claim 1  wherein the compatible device comprises a plurality of registers and an implementation circuit, the implementation circuit capable of decoding and acting on a first or second instruction issued by the data storage device when the compatible device receives an Interrupt Request (INTRQ) issued by the data storage device.  
     
     
         5 . The data storage device of  claim 4  wherein the implementation circuit is hardwired.  
     
     
         6 . The data storage device of  claim 4  wherein the implementation circuit is encoded in software or firmware.  
     
     
         7 . The data storage device of  claim 4  wherein when the first instruction is decoded by the implementation circuit, the implementation circuit causes a value in a register of the compatible device indicated by a value in a first predetermined register of the data storage device to be transmitted to the data storage device and clears the INTRQ signal.  
     
     
         8 . The data storage device of  claim 4  wherein when the second instruction is decoded by the implementation circuit, the implementation circuit causes a value in a fourth predetermined register of the data storage device to be stored into a register of the compatible device indicated by a value in a third predetermined register of the data storage device and clears the INTRQ signal.  
     
     
         9 . A method for a data storage device to control a compatible device through a connecting Integrated Device Electronics (IDE) bus, the data storage device comprising a microprocessor for execution of computer code, a plurality of registers, and a memory comprising computer code capable of controlling the compatible device, the  
       compatible device comprising an implementation circuit and a plurality of registers, the method comprising: 
 the computer code causing a first or second instruction to be stored in a first predetermined register of the data storage device;  
 the computer code causing an Interrupt Request (INTRQ) signal to be transmitted from the data storage device to the compatible device;  
 the compatible device receiving the INTRQ;  
 the implementation circuit decoding and acting on the control instruction; and  
 the compatible device clearing the INTRQ signal.  
 
     
     
         10 . The method of  claim 9  wherein when the implementation circuit decodes the first instruction, acting on the first instruction comprises: 
 the implementation circuit causing a value in a register of the compatible device indicated by a value in a first predetermined register of the data storage device to be transmitted to the data storage device and clearing the INTRQ signal.  
 
     
     
         11 . The method of  claim 9  wherein when the implementation circuit decodes the second instruction, acting on the second instruction comprises: 
 the implementation circuit causing a value in a fourth predetermined register of the data storage device to be stored into a register of the compatible device indicated by a value in a third predetermined register of the data storage device and clearing the INTRQ signal.  
 
     
     
         12 . The method of  claim 9  wherein the compatible device is a bridge, the bridge connected to a host computer system.  
     
     
         13 . The method of  claim 9  wherein the implementation circuit is hardwired.  
     
     
         14 . The method of  claim 9  wherein the implementation circuit is encoded in software or firmware.  
     
     
         15 . A bridge for use in a Host-Bridge-Device system, the bridge connected to the device by an Integrated Device Electronics (IDE) bus, the device comprising a plurality of registers, a microprocessor, and memory comprising computer code capable of issuing a first or second instruction to the bridge, the bridge comprising: 
 a plurality of resisters; and    an implementation circuit capable of decoding and acting upon the first or second instruction issued by the device when the bridge receives an Interrupt Request (INTRQ) issued by the device.    
     
     
         16 . The bridge of  claim 15  wherein when the implementation circuit decodes the first instruction, acting on the first instruction comprises the implementation circuit causing a value in a register of the bridge indicated by a value in a first predetermined register of the device to be transmitted to the device and clearing the INTRQ signal.  
     
     
         17 . The bridge of  claim 15  wherein when the implementation circuit decodes the second instruction, acting on the second instruction comprises the implementation circuit causing a value in a fourth predetermined register of the device to be stored into a register of the bridge indicated by a value in a third predetermined register of the device and clearing the INTRQ signal.  
     
     
         18 . The bridge of  claim 15  wherein the device is a hard disk drive or an optical disc drive.  
     
     
         19 . The bridge of  claim 15  wherein the implementation circuit in hardwired.  
     
     
         20 . A device that controls the bridge of  claim 15  by issuing the first or second instruction to the bridge.