Apparatus for variable word length computing in an array processor

Abstract

A computational unit comprises a processor having a plurality of processing elements, each having an arithmetic logic unit, and a controller for controlling the processor elements. The processor can provide a respectivef bit of a multiple bit word to each of the processor elements and enables signals to be transmitted between the arithmetic logic units to enable the units to perform a parallel operation on the bits of the multiple bit word. Extension circuitry is provided for selectively coupling one or more computational units together to combine their parallel processing capability.

1 . A circuit comprising a processor having a plurality of processor elements, each having an arithmetic logic unit, and a controller for controlling said processor elements, means for providing a respective bit of a multiple bit word to each of said processor elements, and transmission means for enabling signals to be transmitted between said arithmetic logic units, to enable said units to perform a parallel operation on the bits of said multiple bit word.  
     
     
         2 . A circuit as claimed in  claim 1 , wherein each arithmetic logic unit has an output and an input, and said transmission means includes means for coupling the output of each ALU directly to the input of its adjacent ALU which processes a higher order bit.  
     
     
         3 . A circuit as claimed in  claim 1 , wherein said transmission means includes means for coupling the output of the ALU for processing the most significant bit of the multiple bit word directly to the input of the ALU for processing the least significant bit of the multiple bit word.  
     
     
         4 . A circuit as claimed in  claim 1 , wherein the processor element for processing the MSB of the multiple bit word has an input, and the transmission means includes coupling means for coupling the output of the ALU for processing the LSB directly to the input of MSB processing element.  
     
     
         5 . A circuit as claimed in  claim 1 , further comprising a memory coupleable to each of said processor elements.  
     
     
         6 . A die containing a circuit as claimed in  claim 1 .  
     
     
         7 . A circuit comprising a plurality of computational units, each having at least one processor element and extension means for switchably enabling the transmission of signals between said computational units to enable said units to perform a parallel operation on a multiple bit word wherein at least one bit of said word is provided to each computational unit.  
     
     
         8 . A circuit as claimed in  claim 7 , wherein said extension means is capable of coupling the output of the processor element that processes the highest order bit of a computational unit to another computational unit that processes the next higher order bit.  
     
     
         9 . A circuit as claimed in  claim 8 , wherein said extension means is capable of coupling said output to the input of the processor element that processes the next higher order bit of said other computational unit.  
     
     
         10 . A circuit as claimed in  claim 9 , wherein said processor element that processes said highest order bit includes an arithmetic logic unit, and said output comprises the output of said arithmetic logic unit.  
     
     
         11 . A circuit as claimed in  claim 9 , wherein said processor element that processes said higher order bit has an arithmetic logic unit, and said input comprises an input to said arithmetic logic unit.  
     
     
         12 . A circuit as claimed in  claim 7 , wherein said extension means includes a selector switch for selectively coupling said input to one of said output and a port capable of receiving a bit from said other computational unit, or another computational unit.  
     
     
         13 . A circuit as claimed in  claim 7 , wherein said extension means is capable of coupling the output of the processor element that processes the lowest order bit of a computational unit to another computational unit that processes the next lower order bit.  
     
     
         14 . A circuit as claimed in  claim 13 , wherein said extension means is capable of coupling said output to the input of the processor element that processes the next lower order bit of said other computational unit.  
     
     
         15 . A circuit as claimed in  claim 14 , wherein said processor element that processes said lowest order bit includes an arithmetic logic unit, and said output comprises the output of said arithmetic logic unit.  
     
     
         16 . A circuit as claimed in  claim 15 , wherein said extension means includes a selector switch for selectively coupling said input to one of said output and a port for receiving another bit either from said other computational unit that processes the lower order bit or from another computational unit.  
     
     
         17 . A circuit as claimed in  claim 7 , wherein said extension means is capable of coupling the output of the processor element that processes the most significant bit of the multi-bit word to at least one other computational unit that processes one or more bits of said multi-bit word.  
     
     
         18 . A circuit as claimed in  claim 17 , wherein said extension means is capable of coupling the output of said processor element that processes the most significant bit of the multi-bit word to the computational unit that processes the least significant bit of the multi-bit word.  
     
     
         19 . A circuit as claimed in  claim 7 , wherein extension means includes a selector switch for selectively coupling one of the output of the processor element of a computational unit that processes the highest order bit of that computational unit and an output of the processor element that processes the highest order bit of another computational unit, the highest order bit of the other computational unit being higher than the highest order bit of the one computational unit, to an output port coupled to said one computational unit.  
     
     
         20 . A circuit as claimed in  claim 7 , wherein said extension means is capable of coupling the output of the processor element that processes the least significant bit of the multi-bit word to at least one other computational unit that processes one or more bits of said multi-bit word.  
     
     
         21 . A circuit as claimed in  claim 20 , wherein said extension means is capable of coupling the output of the processor element that processes the least significant bit of the multi-bit word to the computational unit that processes the most significant bit of the multiple bit word.  
     
     
         22 . A circuit as claimed in  claim 7 , comprising a selector switch for selectively coupling one of the output of the processor element that processes the lowest order bit of a computational unit and the output of a processor element that processes the lowest order bit of another computational unit, wherein the lowest order bit of the other computational unit is lower than the one computational unit, to a port coupled to the one computational unit or to a computational unit that processes one or more higher order bits than the one computational unit.  
     
     
         23 . A circuit as claimed in  claim 7 , comprising a first CU and a second CU, said first CU having a plurality of processor elements each having an arithmetic logic unit arranged together for performing parallel operations on multiple bit data, and wherein said extension means is arranged to enable a bit output from the MSB ALU of the first CU to be transmitted to the input of the LSB ALU of the second CU.  
     
     
         24 . A circuit as claimed in  claim 7 , comprising a first CU and a second CU, said second CU having a plurality of processor elements, each having an arithmetic logic unit arranged together for performing parallel operations on multiple bit data, and wherein said extension means is arranged to enable a bit output from the MSB ALU of the second CU to be transmitted to the input of the LSB ALU of the first CU.  
     
     
         25 . A circuit as claimed in  claim 7 , comprising a first CU and a second CU, the first CU having a plurality of processor elements, each having arithmetic logic unit arranged together for performing parallel operations on multiple bit data, and wherein said extension means is arranged to enable a bit output from the LSB ALU of the first CU to be transmitted to the second CU.  
     
     
         26 . A circuit as claimed in  claim 25 , wherein said second CU comprises a plurality of processing elements, and said extension means is arranged to enable a bit from said LSB ALU of said first CU to be transmitted to the input of the MSB ALU of said second CU.  
     
     
         27 . A circuit as claimed in  claim 7 , comprising a first CU and a second CU, said first and second CUs having a plurality of processor elements, each having an arithmetic logic unit arranged together for performing parallel operations on multiple bit data, and wherein said extension means enables the output of the MSB ALU of the second CU to be coupled to the input of the LSB ALU of the first CU.