Protection circuit against voltage or current spikes, and clock circuit using a protection circuit of this kind

Abstract

A circuit ( 200 ) for protection against voltage or current spikes receives an initial clock signal (CI) and transmits at least one resultant clock signal (CN 1 , CN 2 , CP 1 , CP 2 ) to a downstream circuit. This resultant clock signal is inactive if a random voltage or current spike appears upstream. This averts the possibility of disturbing the operation of the downstream circuit. Application to the protection of clock circuits for integrated circuits.

What is claimed is:  
     
         1 . A protection circuit ( 200 ) to receive an initial clock signal (CI) and send at least one resultant clock signal (CN 1 , CN 2 , CP 1 , CP 2 ) to a downstream circuit, the protection circuit comprising: 
 an input circuit ( 210 ) receiving the initial clock signal (CI) and producing two intermediate clock signals (CK 1 , CK 2 ) that are images of the initial clock signal (CI),    a recombination circuit ( 220 ) to give a first resulting clock signal (CN 1 ) that is: 
 the image of the intermediate signals (CK 1 , CK 2 ) if said intermediate signals are identical, or  
 inactive if the intermediate signals (CK 1 , CK 2 ) are different from each other.  
   
     
     
         2 . A protection circuit according to  claim 1 , wherein the input circuit ( 210 ) comprises: 
 a first buffer ( 211 ) comprising an input to which the initial clock signal (CI) is applied, and an output to give one of the intermediate clock signals (CK 1 , CK 2 ),    a second buffer ( 212 ) comprising an input connected to the input of the first buffer ( 211 ) and an output to give the other one of the intermediate signals.    
     
     
         3 . A protection circuit according to  claim 1  or  claim 2 , wherein the recombination circuit ( 220 ) comprises a first complex inverter ( 310 ,  410 ,  510 ) comprising a first input ( 311 ,  411 ,  511 ) and a second input ( 312 ,  412 ,  512 ) to receive respectively both of the intermediate signals (CK 1 , CK 2 ), and an output ( 313 ,  413 ,  513 ) at which the first resultant clock signal (CN 1 ) is given, the first complex inverter ( 310 ,  410 ,  510 ) also comprising: 
 a first P type transistor (T 1 ), receiving a power supply voltage (VDD) at a source,  
 a second P type transistor (T 2 ), one source of which is connected to a drain of the first transistor (T 1 ),  
 a third N type transistor (T 3 ), one drain of which is connected to a drain of the second transistor (T 2 ),  
 a fourth N type transistor (T 4 ), one drain of which is connected to a source of the third transistor (T 3 ) and a source of which is connected to a ground (GND) of the circuit,  
 a gate of the premier transistor (T 1 ) and a gate of the third transistor (T 3 ) being connected together to one of the inputs of the first complex inverter, a gate of the second transistor (T 2 ), a gate of the fourth transistor (T 4 ) being connected together to the other of the inputs of the first complex inverter, and common drain of the second transistor (T 2 ) and of the third transistor (T 3 ) being connected to the output of the first complex inverter.  
 
     
     
         4 . A protection circuit according to  claim 3 , wherein the recombination circuit ( 220 ) also comprises a second complex inverter ( 320 ,  520 ), comprising a first input and a second input to respectively receive both the intermediate signals (CK 1 , CK 2 ), and an output at which a second resultant clock signal (CN 2 ) is given.  
     
     
         5 . A protection circuit according to  claim 4 , wherein the recombination circuit ( 220 ) also comprises a third complex inverter ( 330 ), comprising a first input and a second input to respectively receive the first resultant clock signal (CN 1 ) and the second resultant clock signal (CN 2 ), and an output at which a third resultant clock signal (CP 1 ) is given.  
     
     
         6 . A protection circuit according to  claim 4 , wherein the recombination circuit ( 220 ) also comprises a first simple inverter ( 530 ), comprising an input to receive the first resultant clock signal (CN 1 ), and an output at which the third resultant clock signal (CP 1 ) is given, the first simple inverter ( 530 ) also comprising: 
 a fifth P type transistor (T 5 ) receiving a power supply voltage (VDD) at a source, and    a sixth N type transistor (T 6 ), a drain of which is connected to a drain of the fifth transistor (T 5 ), and a source of which is connected to the ground of the circuit (GND),    a gate of the fifth transistor (T 5 ) and a gate of the sixth transistor (T 6 ) being connected together to the input of the first simple inverter ( 530 ), the common drain of the fifth transistor (T 5 ) and of the sixth transistor (T 6 ) being connected to the output of the first simple inverter ( 530 ).    
     
     
         7 . A protection circuit according to  claim 6 , wherein the recombination circuit ( 220 ) also comprises a second simple inverter ( 540 ), comprising an input to receive the second resultant clock signal (CN 2 ), and an output at which a fourth resultant clock signal (CP 1 ) is given.  
     
     
         8 . A protection circuit according to  claim 3 , also comprising the first simple inverter ( 430 ) comprising an input to which one of the intermediate signals (CK 1 ) is applied, the first simple inverter ( 430 ) comprising an output at which the second resultant clock signal (CN 2 ) is given.  
     
     
         9 . A protection circuit according to  claim 8 , also comprising the second simple inverter ( 420 ) comprising an input connected to the output of the first complex inverter ( 410 ) and an output at which the third resultant output signal (CP 1 ) is produced.  
     
     
         10 . A protection circuit according to any of the claims  8  or  9 , also comprising a third simple inverter ( 440 ) comprising an input connected to the output of the first simple inverter ( 430 ) and an output at which the fourth resultant clock signal (CP 2 ) is produced.  
     
     
         11 . A clock circuit for an integrated circuit, comprising a protection circuit according to one of the  claims 1  to  10 .  
     
     
         12 . A clock circuit according to  claim 11 , wherein the protection circuit is connected between a circuit using a clock signal and a part of an arm of the clock circuit giving said clock signal.