Digital electronic circuit for use in implementing digital logic functions

Abstract

A digital electronic circuit having first and second sections. The first section is adapted to transmit one of N input signals. The second section is adapted to receive the signal transmitted by the first section and one or more control signals. The second section is configured to output either an inverse of the signal transmitted by the first section or a logical 0, or to output either an inverse of the signal transmitted by the first section or a logical 1. The second section also may be selectively configurable.

We claim:  
     
         1 . A CMOS digital electronic circuit comprising: 
 a first section adapted to transmit one of N input signals; and    a second section selectively configurable in either a first or a second configuration, wherein the second section is adapted to receive the signal transmitted by the first section and one or more control signals, and to output either an inverse of the signal transmitted by the first section or a logical 0 when in the first configuration, or to output either an inverse of the signal transmitted by the first section or a logical 1 when in the second configuration, the output in either configuration being responsive to the one or more control signals, and wherein the second section includes no more than six transistors.    
     
     
         2 . The circuit of  claim 1 , wherein the output of the second section is responsive to two control signals.  
     
     
         3 . The circuit of  claim 1 , wherein the output of the second section is responsive to one control signal.  
     
     
         4 . The circuit of  claim 1 , wherein the first section comprises an N:1 TGM multiplexer.  
     
     
         5 . The circuit of  claim 4 , wherein the TGM multiplexer is arranged in a serial cascade structure.  
     
     
         6 . The circuit of  claim 1 , wherein the second section includes no more than four transistors.  
     
     
         7 . The circuit of  claim 6 , wherein the first section comprises an N:1 TGM multiplexer.  
     
     
         8 . The circuit of  claim 7 , wherein the TGM multiplexer is arranged in a serial cascade structure.  
     
     
         9 . A method of digital electronic circuit design to produce desired digital output values in response to combinations of five digital input values (I1, I2, S1, X, Y), the method comprising: 
 deciding upon a plurality of digital output values Q, one for each combination of digital input values;    selecting a CMOS circuit having at least one selectively configurable section comprising no more than twelve transistors, wherein the section includes five input signal nodes and at least one output signal node; and    configuring the section to output Q at the output signal node according to the combination of digital input values at the corresponding input signal nodes.    
     
     
         10 . The method of  claim 9 , wherein the selectively configurable section includes a 2:1 multiplexer.  
     
     
         11 . A circuit for use in multiplexer-implemented logic, comprising: 
 a plurality of multiplexing stages, each including at least first and second input nodes adapted to receive input signals, at least one control node adapted to receive a control signal, and an output node adapted to produce an output signal;    wherein the plurality of multiplexing stages are hierarchically arranged so that the output node of each multiplexing stage except the final stage is connected to the first input node of the next higher multiplexing stage; and    wherein the final multiplexing stage is configured so that,    if the control signal on the control node of the final stage is equivalent to a first logic value, then the output signal produced on the output node of the final stage is the inverse of the input signal on the first input node of the final stage, and    if the control signal on the control node of the final stage is equivalent to the inverse of the first logic value, then if the input signal on the second input node of the final stage is equivalent to the inverse of the first logic value, then the output signal produced on the output node of the final stage is the first logic value,    else the output signal produced on the output node of the final stage is the inverse of the input signal on the first input node of the final stage.    
     
     
         12 . The digital logic circuit of  claim 11 , wherein the plurality of multiplexing stages include a plurality of TGM's arranged in a serial cascade structure.  
     
     
         13 . The digital logic circuit of  claim 11 , wherein the final multiplexing stage comprises no more than six transistors.  
     
     
         14 . The digital logic circuit of  claim 13 , wherein the final multiplexing stage includes CMOS transistors.  
     
     
         15 . The digital logic circuit of  claim 11 , wherein the final multiplexing stage is selectively configurable between a first configuration where the first digital logic value is a 1, and a second configuration where the first digital logic value is a 0.  
     
     
         16 . The digital logic circuit of  claim 11 , wherein the final multiplexing stage is selectively reconfigurable so that 
 if the input signal on the second input node of the final stage is equivalent to the first logic value, then the output signal produced on the output node of the final stage is the inverse of the first logic value,    else the output signal produced on the output node of the final stage is the inverse of the input signal on the first input node of the final stage.    
     
     
         17 . An electronic circuit for use in digital logic design, comprising: 
 means for selecting one of N input signals; and    means, controllable by one or more control signals, for transmitting to an output node either an inverse of the selected input signal or an inverse of the one or more control signals.    
     
     
         18 . The circuit of  claim 17 , wherein the means for transmitting is selectively configurable between a first configuration where the constant logic value is a 0, and a second configuration where the constant logic value is a 1.  
     
     
         19 . The circuit of  claim 17 , wherein the means for transmitting includes no more than six transistors.  
     
     
         20 . The circuit of  claim 17 , wherein the means for selecting includes a 2:1 multiplexer.  
     
     
         21 . The circuit of  claim 17 , wherein the means for selecting includes a 3:1 multiplexer.  
     
     
         22 . The circuit of  claim 17 , wherein the means for selecting includes a 4:1 multiplexer.  
     
     
         23 . An electronic circuit comprising: 
 a multiplexer configured to transmit a selected one of N input signals, wherein the multiplexer includes one or more TGM's arranged in a serial cascade structure;    output means for receiving the signal transmitted by the multiplexer and outputting an inverse of the signal; and    control means for enabling and disabling the output means in response to one or more control signals.    
     
     
         24 . The circuit of  claim 23 , wherein the control means includes means for outputting a logic signal when the output means is disabled.  
     
     
         25 . The circuit of  claim 24 , wherein the control means is selectively configurable to output either a logical 0 or a logical 1.  
     
     
         26 . The circuit of  claim 25 , wherein the logic signal is an inverse of the one or more control signals.  
     
     
         27 . The circuit of  claim 23 , wherein the output means includes an inverter.  
     
     
         28 . The circuit of  claim 23 , wherein the multiplexer is a 2:1 multiplexer.  
     
     
         29 . The circuit of  claim 23 , wherein the multiplexer is a 3:1 multiplexer.  
     
     
         30 . The circuit of  claim 24 , wherein the multiplexer is a 4:1 multiplexer.  
     
     
         31 . An electronic digital function generator comprising: 
 a first section including a serial cascade TGM multiplexer having an output node and configured to transmit one of N input signals to the output node depending on N-1 select signals; and    a second section including    an inverter with an input node and an output node, wherein the input node of the inverter is connected to the output node of the first section, and    a control circuit with one or more control nodes adapted to receive one or more digital control signals, wherein the control circuit is configured to enable the inverter when the one or more digital control signals are in a first state, and wherein the control circuit is configured to disable the inverter and connect the output node to at least one of VDD and Ground when the one or more digital control signals are in a state different than the first state.    
     
     
         32 . The electronic digital function generator of  claim 31 , wherein the first section comprises a 3:1 serial cascade TGM multiplexer.  
     
     
         33 . The electronic digital function generator of  claim 31 , wherein the second section includes no more than six transistors.  
     
     
         34 . The electronic digital function generator of  claim 33 , wherein the second section includes six CMOS transistors.  
     
     
         35 . The electronic digital function generator of  claim 31 , wherein the control circuit is selectively configurable in either a first configuration in which the control circuit disables the inverter when the digital control signals are all logical 1's, and a second configuration in which the control circuit disables the inverter when the digital control signals are all logical 0's.  
     
     
         36 . The electronic digital function generator of  claim 31 , wherein the first section comprises a 4:1 serial cascade TGM multiplexer.  
     
     
         37 . A CMOS digital electronic circuit comprising: 
 a first section adapted to transmit one of N input signals; and    a second section adapted to receive the signal transmitted by the first section and two control signals, and to output either an inverse of the signal transmitted by the first section or a logical 0, the output being responsive to the two control signals, and wherein the second section includes no more than six transistors.    
     
     
         38 . The circuit of  claim 37 , where the first section is configured without feedback or fan-out, and where the second section is configured without feedback to the first section.  
     
     
         39 . A CMOS digital electronic circuit comprising: 
 a first section adapted to transmit one of N input signals; and    a second section adapted to receive the signal transmitted by the first section and two control signals, and to output either an inverse of the signal transmitted by the first section or a logical 1, the output being responsive to the two control signals, and wherein the second section includes no more than six transistors.    
     
     
         40 . The circuit of  claim 39 , where the first section is configured without feedback or fan-out, and where the second section is configured without feedback to the first section.