US2004245574A1PendingUtilityA1

ESD protection device with thick poly film and method for forming the same

37
Priority: Apr 25, 2003Filed: Apr 23, 2004Published: Dec 9, 2004
Est. expiryApr 25, 2023(expired)· nominal 20-yr term from priority
Inventors:Ming-Dou KerChih-Kang DengTang-Kui TsengAn ShihSheng-Chieh Yang
H10D 89/811H10D 89/611H10D 86/40H10D 62/117H10D 86/427H10D 86/60
37
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

An ESD protection device with thicker polysilicon film, an electronic apparatus having the same, and a method for manufacturing the same are provided. The ESD protection device can be a diode or a MOS transistor with a thicker polysilicon film employed in an ESD protection circuit to protect an electronic apparatus. The electronic apparatus includes a substrate having a device area and an ESD protection circuit area. A first polysilicon film of a first thickness is formed on the device area of the substrate, so as to form an electronic device. A second polysilicon film of a second thickness is formed on the ESD protection circuit area, so as to form an ESD protection device. The second thickness, which is preferably about in the range of 100 to 500 nanometers, is thicker than the first thickness.

Claims

exact text as granted — not AI-modified
What is claimed is:  
     
         1 . An electrostatic discharge (ESD) protection device in an ESD protection circuit to protect an electronic apparatus, comprising: 
 a substrate;    a polysilicon film of a thickness in a range of about 100 to 500 nanometers formed on said substrate; and    source/drain regions separated by a channel formed in said polysilicon film.    
     
     
         2 . The ESD protection device according to  claim 1 , wherein said substrate is selected from a group consisting of a glass substrate, a quartz substrate, and a combination thereof.  
     
     
         3 . The ESD protection device according to  claim 1  further comprising a gate dielectric layer and a gate electrode, wherein said ESD protection device is arranged in an I/O pad of said electronic apparatus.  
     
     
         4 . An ESD protection device in an ESD protection circuit to protect an electronic apparatus, comprising: 
 a substrate;    a polysilicon film of a thickness in a range of about 100 to 500 nanometers formed on said substrate;    an n-type doped region formed in said polysilicon film; and    a p-type doped region formed in said polysilicon film.    
     
     
         5 . The ESD protection device according to  claim 4 , wherein said n-type doped region is adjacent to said p-type doped region to form a PN diode.  
     
     
         6 . The ESD protection device according to  claim 4  further comprising an intrinsic region between said n-type doped region and said p-type doped region to form a PIN diode.  
     
     
         7 . The ESD protection device according to  claim 4 , wherein said substrate is selected from a group consisting of a glass substrate, a quartz substrate, and a combination thereof.  
     
     
         8 . The ESD protection device according to  claim 4 , wherein said ESD protection device is arranged in an I/O pad of said electronic apparatus.  
     
     
         9 . An electronic apparatus having an ESD protection device with thicker polysilicon film, comprising: 
 a substrate having a device area and an ESD protection circuit area;    a first polysilicon film of a first thickness formed on said device area, so as to form an electronic device; and    a second polysilicon film of a second thickness formed on said ESD protection circuit area, so as to form said ESD protection device, wherein said second thickness is larger than said first thickness.    
     
     
         10 . The electronic apparatus according to  claim 9 , wherein said electronic device comprises first source/drain regions separated by a first channel formed in said first polysilicon film.  
     
     
         11 . The electronic apparatus according to  claim 10 , wherein said ESD protection device comprises second source/drain regions separated by a second channel formed in said second polysilicon film.  
     
     
         12 . The electronic apparatus according to  claim 10  further comprising an n-type doped region and a p-type doped region in said second polysilicon film to form a PN diode.  
     
     
         13 . The electronic apparatus according to  claim 12  further comprising an intrinsic region between said n-type doped region and said p-type doped region in said second polysilicon film to form a PIN diode.  
     
     
         14 . The electronic apparatus according to  claim 9 , wherein said second thickness is in a range of about 100 to 500 nanometers.  
     
     
         15 . A method for forming an ESD protection device in an ESD protection circuit, comprising: 
 providing a substrate having a device area and an ESD protection circuit area;    forming a first polysilicon film of a first thickness on said device area of said substrate, so as to form an electronic device; and    forming a second polysilicon film of a second thickness on said ESD protection circuit area of said substrate, so as to form said ESD protection device, wherein said second thickness is larger than said first thickness.    
     
     
         16 . The method according to  claim 15 , wherein said step of forming said first and second polysilicon films comprises: 
 forming said second polysilicon film on said substrate to cover said device area and said ESD protection circuit area;    forming a patterned photoresist layer on said second polysilicon film to expose a portion of said second polysilicon film corresponding to said device area; and    etching said second polysilicon film to reach said first thickness by using said patterned photoresist layer as a mask.    
     
     
         17 . The method according to  claim 15 , wherein said step of forming said first and second polysilicon films comprises: 
 forming a polysilicon film of a third thickness on said substrate to cover said device area and said ESD protection circuit area;    forming a patterned photoresist layer on said polysilicon film to expose a portion of said polysilicon film corresponding to said device area;    etching said polysilicon film to expose said substrate by using said patterned photoresist layer as a mask;    removing said patterned photoresist layer; and    depositing said first polysilicon film on said substrate, wherein said second thickness equals said third thickness plus said first thickness.    
     
     
         18 . The method according to  claim 15  further comprising forming first source/drain regions separated by a fist channel in said first polysilicon film.  
     
     
         19 . The method according to  claim 18  further comprising forming second source/drain regions separated by a second channel in said second polysilicon film.  
     
     
         20 . The method according to  claim 18  further comprising forming an n-type doped region and a p-type doped region in said second polysilicon film to form a PN diode.  
     
     
         21 . The method according to  claim 20  further comprising forming an intrinsic region between said n-type doped region and said p-type doped region in said second polysilicon film to form a PIN diode.  
     
     
         22 . The method according to  claim 15 , wherein said second thickness is in a range of about 100 to 500 nanometers.

Join the waitlist — get patent alerts

Track US2004245574A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.