Process for making a silicon-on-insulator ledge and structures achieved thereby

Abstract

A process of making a partial silicon-on-insulator ledge is disclosed. A deep implantation region is created in a substrate. During a lateral cavity etch, the deep implantation region resists etching. The lateral cavity etch acts to partially isolate an active area above the deep implantation region. The deep implantation region is formed at various process stages according to embodiments. An active device is also disclosed that is achieved by the process. A system is also disclosed that uses the active device.

What is claimed is:  
     
         1 . An electrical device comprising: 
 a semiconductive substrate;    a recess disposed in the substrate, wherein the recess includes a recess wall and a recess bottom;    a lateral cavity disposed below the recess wall and at the recess bottom, wherein the lateral cavity has a depth in a range from about 0.12 microns to about 0.02 microns and wherein the lateral cavity includes a faceted surface that follows crystallographic planes in the semiconductive substrate; and    an active area above the lateral cavity, wherein the active area is partially isolated from the substrate by the lateral cavity.    
     
     
         2 . The electrical device according to  claim 1 , further including: 
 a chip package, wherein the substrate is disposed in the chip package.    
     
     
         3 . The electrical device according to  claim 1 , further including: 
 a chip package, wherein the substrate is disposed in the chip package; and    a host, wherein the chip package is disposed in the host.    
     
     
         4 . The electrical device according to  claim 1 , further including: 
 a chip package, wherein the substrate is disposed in the chip package; and    a host, wherein the chip package is disposed in the host, wherein the host includes a memory module.    
     
     
         5 . The electrical device according to  claim 1  further including: 
 a chip package, wherein the substrate is disposed in the chip package; and  
 a host, wherein the chip package is disposed in the host, wherein the host includes a memory module; and  
 an electronic system, wherein the memory module is disposed in the electronic system.  
 
     
     
         6 . The electrical device according to  claim 1 , further including: 
 a chip package, wherein the substrate is disposed in the chip package;    a host, wherein the chip package is disposed in the host, wherein the host includes a dynamic random access memory module; and    an electronic system, wherein the dynamic random access memory module is disposed in the electronic system.    
     
     
         7 . The electrical device according to  claim 1 , further including: 
 a chip package, wherein the substrate is disposed in the chip package;    a host, wherein the chip package is disposed in the host; and    an electronic system, wherein the host is disposed in the electronic system.    
     
     
         8 . A computer system, comprising: 
 a processor;    a memory system coupled to the processor;    an input/output (I/O) circuit coupled to the processor and the memory system; and    a partially isolated structure disposed in the processor or the memory system, the partially isolated structure including:    a semiconductive substrate;    a recess disposed in the substrate, wherein the recess includes a recess wall and a recess bottom;    a lateral cavity disposed below the recess wall and at the recess bottom, wherein the lateral cavity has a depth in a range from about 0.12 microns to about 0.02 microns and wherein the lateral cavity includes a faceted surface that follows crystallographic planes in the semiconductive substrate; and    an active area above the lateral cavity, wherein the active area is partially isolated from the substrate by the lateral cavity.    
     
     
         9 . The computer system according to  claim 8 , wherein the processor is disposed in a host selected from a clock, a television, a cell phone, a personal computer, an automobile, an industrial control system, an aircraft, and a hand-held.  
     
     
         10 . The computer system according to  claim 8 , wherein the memory system is disposed in a host selected from a clock, a television, a cell phone, a personal computer, an automobile, an industrial control system, an aircraft, and a hand-held.  
     
     
         11 . A storage device comprising: 
 a semiconductive substrate;    a recess disposed in the substrate, wherein the recess includes a recess first wall and a recess second bottom;    a lateral cavity disposed below the recess first wall and at the recess second bottom, wherein the lateral cavity includes a faceted surface that follows crystallographic planes in the semiconductive substrate;    an active area above the lateral cavity, wherein the active area is partially isolated from the substrate by the lateral cavity;    a digit line junction and a storage node junction in the partially isolated active area;    a word line, wherein the word line overlays the partially isolated active area;    a polysilicon plug in electrical contact with the partially isolated active area;    a storage node in electrical contact with the polysilicon plug; and    a digit line coupled to the digit line junction.    
     
     
         12 . The storage device of  claim 11 , wherein the lateral cavity has a depth in a range from about 0.12 microns to about 0.02 microns.  
     
     
         13 . The storage device of  claim 11 , wherein the storage node junction is part of a plurality of two storage node junctions, wherein the polysilicon plug is part of a plurality of two polysilicon plugs, and wherein the storage node is part of a plurality of two storage nodes.  
     
     
         14 . The storage device of  claim 11 , further including: 
 a chip package, wherein the substrate is disposed in the chip package.    
     
     
         15 . An article comprising: 
 a semiconductive substrate;    a recess disposed in the substrate, wherein the recess includes a recess wall and a recess bottom;    a lateral cavity disposed below the recess wall and at the recess bottom, wherein the lateral cavity includes a faceted surface that follows crystallographic planes in the semiconductive substrate;    an active area above the lateral cavity, wherein the active area is partially isolated from the substrate by the lateral cavity; and    a deep implantation region, wherein the deep implantation region extends from the lateral cavity and substantially continuously across and below the active area.    
     
     
         16 . The article of  claim 15 , wherein the lateral cavity has a depth in a range from about 0.12 microns to about 0.02 microns.  
     
     
         17 . The article of  claim 15 , wherein the deep implantation region includes an implanted concentration in a range from about 5E14 atoms/cm 2  to about 5E15 atoms/cm 2 .  
     
     
         18 . The article of  claim 15 , further including: 
 a chip package, wherein the substrate is disposed in the chip package.    
     
     
         19 . An article comprising: 
 a semiconductive substrate;    a recess disposed in the substrate, wherein the recess includes a recess wall and a recess bottom;    a lateral cavity disposed below the recess wall and at the recess bottom, wherein the lateral cavity includes a faceted surface that follows crystallographic planes in the semiconductive substrate;    an active area above the lateral cavity, wherein the active area is partially isolated from the substrate by the lateral cavity;    a shallow implantation region, wherein the shallow implantation region extends from the recess wall and substantially continuously across and below the active area; and    a deep implantation region, wherein the deep implantation region extends from the lateral cavity and substantially continuously across and below the active area.    
     
     
         20 . The article of  claim 19 , wherein the lateral cavity has a depth in a range from about 0.12 microns to about 0.02 microns.  
     
     
         21 . The article of  claim 19 , wherein the deep implantation region includes an implanted concentration in a range from about 5E14 atoms/cm 2  to about 5E15 atoms/cm 2 .  
     
     
         22 . The article of  claim 19 , further including: 
 a chip package, wherein the substrate is disposed in the chip package.    
     
     
         23 . An electrical device comprising: 
 a semiconductive substrate;    a recess disposed in the substrate, wherein the recess includes a recess wall and a recess bottom;    a lateral cavity disposed below the recess wall and at the recess bottom, wherein the lateral cavity has a depth in a range from about 0.12 microns to about 0.02 microns and wherein the lateral cavity includes a faceted surface that follows crystallographic planes in the semiconductive substrate; and    an active area above the lateral cavity, wherein the active area is partially isolated from the substrate by the lateral cavity, wherein the lateral cavity defines a portion of a stem which connects the substrate to the active area, and wherein the stem includes a thickness in a range from about 0.05 micron to about 0.07 micron.    
     
     
         24 . The electrical device of  claim 23 , further including an oxide disposed in the lateral cavity, wherein the oxide includes a thickness in a range from about 0.0005 micron to about 0.1 micron.  
     
     
         25 . The electrical device of  claim 23 , further including: 
 a chip package, wherein the substrate is disposed in the chip package.