Semiconductor processing system

Abstract

A semiconductor processing system includes an intermediate structure ( 37 A, 37 B) disposed between an atmospheric pressure entrance transfer chamber ( 32 ) and a vacuum common transfer chamber ( 36 ). The intermediate structure includes a transfer passage ( 38 A, 38 B) for a target substrate (W) to pass therein. The transfer passage includes a first buffer chamber ( 70 ), a middle transfer chamber ( 72 ), and a second buffer chamber ( 74 ) detachably connected. An additional processing apparatus ( 110, 110 A) is detachably connected to the middle transfer chamber. The intermediate structure is selectively arranged in first or second state. In the first state, the additional processing apparatus ( 110 ) performs a vacuum process, while the first buffer chamber ( 70 ) is a load-lock chamber. In the second state, the additional processing apparatus ( 110 A) performs an atmospheric pressure process, while the second buffer chamber ( 74 ) is a load-lock chamber.

1 . A semiconductor processing system comprising: 
 an entrance transfer chamber with an atmospheric pressure atmosphere, which has a loading port for loading a target substrate into the semiconductor processing system;    a common transfer chamber with a vacuum atmosphere, which is connected to the entrance transfer chamber through an intermediate structure that forms a route for transferring the target substrate;    a plurality of vacuum processing apparatuses connected to the common transfer chamber, each of which is configured to perform a predetermined process on the target substrate within a vacuum atmosphere;    a transfer arm device disposed in the entrance transfer chamber and configured to transfer the target substrate between a portion outside the semiconductor processing system and the intermediate structure; and    a transfer arm device disposed in the common transfer chamber and configured to transfer the target substrate between the intermediate structure and the vacuum processing apparatuses,    wherein the intermediate structure comprises    a transfer passage that connects the entrance transfer chamber and the common transfer chamber to allow the target substrate to pass therein, and includes a first buffer chamber, a middle transfer chamber, and a second buffer chamber connected in series in this order and detachable from each other, such that the first and second buffer chambers are detachably connected to the entrance transfer chamber and the common transfer chamber, respectively,    an additional processing apparatus detachably connected to the middle transfer chamber, and    a transfer arm device disposed in the middle transfer chamber and configured to transfer the target substrate between the first buffer chamber, the additional processing apparatus, and the second buffer chamber; and    the intermediate structure is selectively arranged to be in one of first and second states, the first state being a state where the additional processing apparatus is set to perform a predetermined process on the target substrate within a vacuum atmosphere, while the first buffer chamber is set to be a load-lock chamber for adjusting pressure between atmospheric pressure and vacuum, and the second state being a state where the additional processing apparatus is set to perform a predetermined process on the target substrate within an atmospheric pressure atmosphere, while the second buffer chamber is set to be a load-lock chamber for adjusting pressure between atmospheric pressure and vacuum.    
     
     
         2 . The semiconductor processing system according to  claim 1 , wherein one of the first and second buffer chambers, which is set to be the load-lock chamber, is connected to adjacent chambers on both sides respectively through gate valves.  
     
     
         3 . The semiconductor processing system according to  claim 2 , wherein one of the first and second buffer chambers, which is not set to be the load-lock chamber, is connected to adjacent chambers on both sides respectively through sleeve pipes having no valve function.  
     
     
         4 . The semiconductor processing system according to  claim 2 , wherein one of the first and second buffer chambers, which is not set to be the load-lock chamber, is connected to adjacent chambers on both sides respectively through gate valves, which are kept always open by software control.  
     
     
         5 . The semiconductor processing system according to  claim 1 , wherein the entrance transfer chamber and the first buffer chamber, the first buffer chamber and the middle transfer chamber, the middle transfer chamber and the second buffer chamber, and the second buffer chamber and the common transfer chamber are detachably connected by flanges.  
     
     
         6 . The semiconductor processing system according to  claim 1 , wherein one of the first and second buffer chambers, which is set to be the load-lock chamber, has a degas function of performing a degas process by heating the target substrate, and/or a cooling function of cooling the target substrate.  
     
     
         7 . The semiconductor processing system according to  claim 1 , further comprising a rotary holder disposed in the second buffer chamber to rotate the target substrate by a predetermined angle.  
     
     
         8 . A semiconductor processing system comprising: 
 an entrance transfer chamber with an atmospheric pressure atmosphere, which has a loading port for loading a target substrate into the semiconductor processing system;    a common transfer chamber with a vacuum atmosphere, which is connected to the entrance transfer chamber through first and second intermediate structures that form routes parallel with each other for transferring the target substrate;    a plurality of vacuum processing apparatuses connected to the common transfer chamber, each of which is configured to perform a predetermined process on the target substrate within a vacuum atmosphere;    a transfer arm device disposed in the entrance transfer chamber and configured to transfer the target substrate between a portion outside the semiconductor processing system and the first and second intermediate structures; and    a transfer arm device disposed in the common transfer chamber and configured to transfer the target substrate between the first and second intermediate structures and the vacuum processing apparatuses,    wherein each of the first and second intermediate structures comprises    a transfer passage that connects the entrance transfer chamber and the common transfer chamber to allow the target substrate to pass therein, and includes a first buffer chamber, a middle transfer chamber, and a second buffer chamber connected in series in this order and detachable from each other, such that the first and second buffer chambers are detachably connected to the entrance transfer chamber and the common transfer chamber, respectively,    an additional processing apparatus detachably connected to the middle transfer chamber, and    a transfer arm device disposed in the middle transfer chamber and configured to transfer the target substrate between the first buffer chamber, the additional processing apparatus, and the second buffer chamber.    
     
     
         9 . The semiconductor processing system according to  claim 8 , wherein each of the first and second intermediate structures is selectively arranged to be in one of first and second states, the first state being a state where the additional processing apparatus is set to perform a predetermined process on the target substrate within a vacuum atmosphere, while the first buffer chamber is set to be a load-lock chamber for adjusting pressure between atmospheric pressure and vacuum, and the second state being a state where the additional processing apparatus is set to perform a predetermined process on the target substrate within an atmospheric pressure atmosphere, while the second buffer chamber is set to be a load-lock chamber for adjusting pressure between atmospheric pressure and vacuum.  
     
     
         10 . The semiconductor processing system according to  claim 9 , wherein the first and second intermediate structures are set to be states different from each other, selected from the first and second states.  
     
     
         11 . The semiconductor processing system according to  claim 9 , wherein the first and second intermediate structures are set to be states the same as each other, selected from the first and second states.  
     
     
         12 . The semiconductor processing system according to  claim 9 , wherein, in each of the first and second intermediate structures, one of the first and second buffer chambers, which is set to be the load-lock chamber, is connected to adjacent chambers on both sides respectively through gate valves.  
     
     
         13 . The semiconductor processing system according to  claim 12 , wherein, in each of the first and second intermediate structures, one of the first and second buffer chambers, which is not set to be the load-lock chamber, is connected to adjacent chambers on both sides respectively through sleeve pipes having no valve function.  
     
     
         14 . The semiconductor processing system according to  claim 12 , wherein, in each of the first and second intermediate structures, one of the first and second buffer chambers, which is not set to be the load-lock chamber, is connected to adjacent chambers on both sides respectively through gate valves, which are kept always open by software control.  
     
     
         15 . The semiconductor processing system according to  claim 8 , wherein, in each of the first and second intermediate structures, the entrance transfer chamber and the first buffer chamber, the first buffer chamber and the middle transfer chamber, the middle transfer chamber and the second buffer chamber, and the second buffer chamber and the common transfer chamber are detachably connected by flanges.