Voltage supply interface circuit

Abstract

A monolithic interface circuit for providing a voltage, from a control circuit supplied by a supply voltage referenced to a reference voltage, to a terminal likely to be at a high voltage with respect to the reference voltage, comprising a high-voltage N-channel MOS transistor having its gate intended to receive a control signal referenced to the reference voltage and having its source intended to be connected to the reference voltage, and a high-voltage PNP transistor having its base connected to the drain of the MOS transistor, having its emitter intended to receive the supply voltage and having its collector intended to provide a voltage to the terminal likely to be at a high voltage.

What is claimed is:  
     
         1 . A monolithic interface circuit for providing a voltage, from a control circuit supplied by a supply voltage referenced to a reference voltage, to a terminal likely to be at a high voltage with respect to the reference voltage, comprising: 
 a high-voltage N-channel MOS transistor having its gate intended to receive a control signal referenced to the reference voltage and having its source intended to be connected to the reference voltage, and    a high-voltage PNP transistor having its base connected to the drain of the MOS transistor, having its emitter intended to receive the supply voltage, and having its collector intended to provide a voltage to the terminal likely to be at a high voltage.    
     
     
         2 . The monolithic interface circuit of  claim 1 , wherein said terminal is a control terminal of a switch.  
     
     
         3 . The monolithic interface circuit of  claim 1 , wherein the high-voltage MOS transistor and the high-voltage PNP transistor are vertical transistors formed in an N-type silicon substrate surrounded with a P-type insulating wall, comprising: 
 on its upper surface side, a first P-type region and a P-type well having its lateral portions formed of lightly-doped P-type regions, this well containing N-type source regions extending into the lightly-doped P-type areas, the upper surface of the lightly-doped P-type areas being coated with an insulated gates, and    on its lower surface side, a second P-type region facing the first P-type region and in contact with the insulating wall, the rear surface portion in which the substrate is apparent being coated with an insulating layer.    
     
     
         4 . The monolithic interface circuit of  claim 3 , wherein the high-voltage PNP transistor is arranged around the high-voltage MOS transistor.