Lock detector for phase locked loops

Abstract

A detector circuit for determining whether synchronization lock has been optimally achieved in feedback-type control systems. The detector circuit evaluates an error signal developed by a phase/frequency detector and compares the absolute magnitude of the error signal to a first threshold signal corresponding to a magnitude metric. When the value of the error signal is less than the magnitude threshold value, an event signal initiates a time interval counter which continues counting so long as the error signal remains below the magnitude threshold value. The time interval counter continues until it counts to a second threshold value corresponding to a timing metric. At this point, synchronization lock is declared.

1 . An interference rejection filter for removing undesirable frequency components in a broadband signal disposed in a given frequency range, the filter comprising: 
 a plurality of at least three filter stages connected in tandem, each filter stage having a multiplier with first and second inputs and an output, an oscillator coupled to the first input, a baseband DC canceler stage coupling the output of each filter stage to the second input of the next filter stage except for the output of the last filter stage;    means for coupling the broadband signal to the input of the first stage;    a frequency conversion stage; and    means for coupling the output of the third last stage to the frequency conversion stage.    
     
     
         2 . The filter of  claim 1 , in which the frequency conversion stage returns the broadband signal without the undesirable frequency components to the given frequency range.  
     
     
         3 . The filter of  claim 1 , in which the filter stages each have a bandwidth that corresponds to the given frequency range.  
     
     
         4 . The filter of  claim 1 , in which the multipliers are complex multipliers.  
     
     
         5 . The filter of  claim 1 , in which the broadband signal is an HDTV signal.  
     
     
         6 . The filter of  claim 1 , in which the oscillator is a direct digital frequency synthesizer (DDFS)  
     
     
         7 . The filter of  claim 6 , in which the oscillator of the first filter stage has a frequency of 1.75 MHz.  
     
     
         8 . The filter of  claim 1 , in which the plurality of filter stages is three in number.  
     
     
         9 . The filter of  claim 8 , in which the oscillator of the first filter stage has a frequency of 3.58 MHz.  
     
     
         10 . The filter of  claim 9 , in which the oscillator of the first filter stage has a frequency of 0.92 MHz.