US2004230836A1PendingUtilityA1

Hardware implementation of process-based security protocol

33
Priority: Feb 1, 2002Filed: Feb 10, 2004Published: Nov 18, 2004
Est. expiryFeb 1, 2022(expired)· nominal 20-yr term from priority
Inventors:Vincent Larsen
G06F 21/6218G06F 2221/2141
33
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

A memory structure stores instructions for a method of providing access for a user to resources through a process. The process includes receiving user identification information and identifying user resource access information associated with the user identification information. The user resource access information includes process resource access information associated with a process. The process determines when an executing process attempts to accesses a specified resource and checks the process resource access information associated with the process when the process attempts to access the specified resource. The process determines if access to the specified resource by the process is permitted and allows the process to access the specified resource if access permission is indicated and denies the process access to the specified resource if access permission is not indicated.

Claims

exact text as granted — not AI-modified
What is claimed is:  
     
         1 . A memory structure storing instructions for a method of providing access for a user to resources through a process, said method comprising the steps of: 
 receiving user identification information;    identifying user resource access information associated with the user identification information, wherein the user resource access information includes process resource access information associated with a process;    determining when an executing process attempts to accesses a specified resource;    checking the process resource access information associated with the process when the process attempts to access the specified resource to determine if access to the specified resource by the process is permitted;    allowing the process to access the specified resource if access permission is indicated; and    denying the process access to the specified resource if access permission is not indicated.    
     
     
         2 . The memory structure of  claim 1 , wherein said memory structure is an integrated circuit.  
     
     
         3 . The memory structure of  claim 2 , wherein said memory structure is a read-only memory integrated circuit.  
     
     
         4 . The memory structure of  claim 3 , wherein said read-only memory integrated circuit is a programmable read-only memory integrated circuit.  
     
     
         5 . The memory structure of  claim 1 , wherein said memory structure is a flash memory structure.  
     
     
         6 . The memory structure of  claim 1 , wherein said memory structure is an optical storage disk.  
     
     
         7 . The memory structure of  claim 1 , wherein said memory structure is a magnetic storage disk.  
     
     
         8 . The memory structure of  claim 1 , further comprising an extended instruction set.  
     
     
         9 . An integrated circuit storing instructions for a method of providing access for a user to resources through a process, said method comprising the steps of: 
 identifying process resource access information associated with a process;    determining when the process attempts to accesses a specified resource;    checking the process resource access information associated with the process when the process attempts to access the specified resource to determine if access to the specified resource by the process is permitted;    allowing the process to access the specified resource if access permission is indicated; and    denying the process access to the specified resource if access permission is not indicated.    
     
     
         10 . The integrated circuit of  claim 9 , wherein said integrated circuit is a read-only memory.  
     
     
         11 . The integrated circuit of  claim 10 , wherein said read-only memory is a programmable read-only memory.  
     
     
         12 . The integrated circuit of  claim 11 , wherein said programmable read-only memory is an erasable programmable read-only memory.  
     
     
         13 . The integrated circuit of  claim 12 , wherein said erasable programmable read-only memory is an electrically erasable programmable read-only memory.  
     
     
         14 . A storage medium storing instructions for a method of providing access for a user to resources through a process, said method comprising the steps of: 
 determining when the process attempts to accesses a specified resource;    checking the process resource access information associated with the process when the process attempts to access the specified resource to determine if access to the specified resource by the process is permitted.    
     
     
         15 . The storage medium of  claim 14 , wherein said storage medium is an integrated circuit.  
     
     
         16 . The storage medium of  claim 14 , wherein said storage medium is a rotating optical storage medium.  
     
     
         17 . The storage medium of  claim 14 , wherein said storage medium is a rotating magnetic storage medium.  
     
     
         18 . The storage medium of  claim 17 , wherein said rotating magnetic storage medium is a floppy disk.  
     
     
         19 . The storage medium of  claim 16 , wherein said rotating magnetic storage medium is a compact disk.  
     
     
         20 . The storage medium of  claim 14 , further comprising an extended instruction set.

Join the waitlist — get patent alerts

Track US2004230836A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.