Multichip wafer level system packages and methods of forming same

Abstract

The present invention defines a packaging implementation providing a multichip multilayer system on a chip solution. Greater integration of a plurality and variety of known good die contained within cavities formed in a separate substrate is achieved. Additional redistribution and interconnect layers above the multichip configuration may be formed with the redistribution layers terminating in electrical connections such as conductive bumps or balls. In one embodiment, the cavities of the substrate receive signal device connections, such as conductive bumps, of a plurality of semiconductor dice in a flip-chip configuration. A portion of the back surface of the substrate is then removed to a depth sufficient to expose the conductive bumps. In another embodiment, the cavities receive the semiconductor dice with the active surface of the semiconductor dice facing up wherein metal layer connections are formed and coupled to bond pads or other electrical connectors of the semiconductor dice.

What is claimed is:  
     
         1 . A method of manufacturing a multichip package comprising: 
 providing a substrate having a top surface and a bottom surface;    forming a plurality of cavities in the top surface of the substrate, each cavity being defined by a base and at least one cavity wall;    providing a plurality of semiconductor dice, each semiconductor die having a back surface and a plurality of signal connection devices on an active surface thereof;    applying a layer of die attach material to the base of each of the plurality of cavities;    placing the plurality of semiconductor dice in the plurality of cavities with the back surfaces thereof facing the base of the plurality of cavities;    forming a first dielectric layer upon the top surface of the substrate and the active surfaces of the semiconductor dice including the plurality of signal connection devices; and    forming a plurality of openings in the first dielectric layer exposing the plurality of signal connection devices.    
     
     
         2 . The method of  claim 1 , further comprising: 
 forming a first circuit connection layer on the first dielectric layer; and    electrically coupling the first circuit connection layer with the plurality of signal connection devices through the plurality of openings;    forming at least one additional dielectric layer over the first dielectric layer and the first circuit connection layer;    forming a plurality of openings in the at least one additional dielectric layer exposing a plurality of connection areas on the first circuit connection layer; and    forming a plurality of conductive bumps in the plurality of openings of the at least one additional dielectric layer and electrically coupling the plurality of conductive bumps with the plurality of connection areas on the first circuit connection layer.    
     
     
         3 . The method of  claim 2 , wherein providing a substrate includes providing a substrate comprising a silicon wafer.  
     
     
         4 . The method of  claim 3 , further comprising forming the plurality of signal connection devices to include bond pads.  
     
     
         5 . The method of  claim 4 , further comprising forming each of the plurality of cavities to exhibit a depth which is substantially equal to or greater than a height of each of the plurality of semiconductor dice.  
     
     
         6 . The method of  claim 5 , wherein applying a layer of die attach material further includes applying a layer of epoxy material.  
     
     
         7 . The method of  claim 5 , wherein applying a layer of die attach material further includes applying a layer of benzocyclobutene.  
     
     
         8 . The method of  claim 5 , wherein applying a layer of die attach material further comprises applying a layer of material exhibiting a dielectric constant of up to about three.