Method and apparatus for high throughput multiplexing of data

Abstract

A method and apparatus for high throughput multiplexing of data is described. It includes a circuit including: A first multiplexer having an output, a first input, a second input, and a selector. A second multiplexer having an output, a first input, a second input, and a selector, the output of the second multiplexer coupled to the first input of the first multiplexer. A third multiplexer having an output, a first input, a second input, and a selector, the output of the third multiplexer coupled to the second input of the first multiplexer; and the selector of the first multiplexer to select an input with a stable signal.

What is claimed is:  
     
         1 . A circuit comprising: 
 a first multiplexer having an output, a first input, a second input, and a selector;    a second multiplexer having an output, a first input, a second input, and a selector, the output of the second multiplexer coupled to the first input of the first multiplexer;    a third multiplexer having an output, a first input, a second input, and a selector, the output of the third multiplexer coupled to the second input of the first multiplexer; and    the selector of the first multiplexer to select an input with a stable signal.    
     
     
         2 . The circuit of  claim 1  wherein: 
 the selector of the second multiplexer to switch when the selector of the first multiplexer switches away from the output of the second multiplexer.  
 
     
     
         3 . The circuit of  claim 2  wherein: 
 the selector of the third multiplexer to switch when the selector of the first multiplexer switches away from the output of the third multiplexer.  
 
     
     
         4 . The circuit of  claim 1  wherein: 
 the selector of the second multiplexer and the selector of the third multiplexer to provide at least one stable input to the first multiplexer.  
 
     
     
         5 . The circuit of  claim 4  wherein: 
 the first input of the second multiplexer to switch only when the first input of the second multiplexer is not routed through to the output of the second multiplexer by the selector of the second multiplexer.  
 
     
     
         6 . The circuit of  claim 5  wherein: 
 the second input of the second multiplexer to switch only when the second input of the second multiplexer is not routed through to the output of the second multiplexer by the selector of the second multiplexer.  
 
     
     
         7 . The circuit of  claim 6  wherein: 
 the first input of the third multiplexer to switch only when the first input of the third multiplexer is not routed through to the output of the third multiplexer by the selector of the third multiplexer.  
 
     
     
         8 . The circuit of  claim 7  wherein: 
 the second input of the third multiplexer to switch only when the second input of the third multiplexer is not routed through to the output of the third multiplexer by the selector of the third multiplexer.  
 
     
     
         9 . The circuit of  claim 2  wherein: 
 the first input of the third multiplexer coupled to the second input of the third multiplexer.  
 
     
     
         10 . A method comprising: 
 selecting between two inputs of a first multiplexer, the two inputs of the first multiplexer being coupled to outputs of a second multiplexer and a third multiplexer, wherein the first, second, and third multiplexers are components of a four-input multiplexing circuit;    selecting between two inputs of the second multiplexer, the selecting of the second multiplexer performed when the selecting of the first multiplexer results in the first multiplexer selecting the output of the third multiplexer; and    selecting between two inputs of the third multiplexer, the selecting of the third multiplexer performed when the selecting of the first multiplexer results in the first multiplexer selecting the output of the second multiplexer.    
     
     
         11 . The method of  claim 10 , wherein: 
 the selecting of the first multiplexer performed in an alternating manner.    
     
     
         12 . The method of  claim 10 , wherein: 
 the selecting of the first multiplexer performed by a clock signal coupled to the four-input multiplexing circuit.    
     
     
         13 . The method of  claim 10 , wherein: 
 the second multiplexer having two inputs coupled to two of the four inputs; and    the third multiplexer having two inputs coupled to two of the four inputs.    
     
     
         14 . The method of  claim 10 , wherein: 
 the selecting of the third multiplexer does not change the output of the third multiplexer.    
     
     
         15 . A system comprising: 
 a processor;    a memory control hub coupled to the processor;    a memory coupled to the memory control hub;    an i/o hub coupled to the memory control hub; and    at least one of the processor, the memory control hub, the memory, and the i/o hub further comprising: a first multiplexer having an output, a first input, a second input, and a selector, a second multiplexer having an output, a first input, a second input, and a selector, the output of the second multiplexer coupled to the first input of the first multiplexer, a third multiplexer having an output, a first input, a second input, and a selector, the output of the third multiplexer coupled to the second input of the first multiplexer, and wherein the selector of the first multiplexer is to choose an input with a stable signal.    
     
     
         16 . A chipset comprising: 
 a memory control hub capable of being coupled to a processor and capable of being coupled to a memory;    an i/o hub coupled to the memory control hub; and    at least one of the memory control hub and the i/o hub further comprising: a first multiplexer having an output, a first input, a second input, and a selector, a second multiplexer having an output, a first input, a second input, and a selector, the output of the second multiplexer coupled to the first input of the first multiplexer, a third multiplexer having an output, a first input, a second input, and a selector, the output of the third multiplexer coupled to the second input of the first multiplexer, and wherein the selector of the first multiplexer is to choose an input with a stable signal.    
     
     
         17 . A circuit comprising: 
 a first multiplexer having an output, a first input, a second input, and a selector;    a second multiplexer having an output, a first input, a second input, and a selector, the output of the second multiplexer coupled to the first input of the first multiplexer;    a third multiplexer having an output, a first input, a second input, and a selector, the output of the third multiplexer coupled to the second input of the first multiplexer; and    the selector of the first multiplexer to select the output of the second multiplexer when the output of the second multiplexer is stable, the multiplexer to select the output of the third multiplexer when the output of the third multiplexer is stable, the output of the second multiplexer stable when the output of the third multiplexer switches, the output of the third multiplexer stable when the output of the second multiplexer switches.    
     
     
         18 . The circuit of  claim 17 , wherein: 
 the selector of the third multiplexer to switch to the first input of the third multiplexer only when the first input of the third multiplexer is stable, the selector of the third multiplexer to switch to the second input of the third multiplexer only when the second input of the third multiplexer is stable; and    the selector of the second multiplexer to switch to the first input of the second multiplexer only when the first input of the second multiplexer is stable, the selector of the second multiplexer to switch to the second input of the second multiplexer only when the second input of the second multiplexer is stable.    
     
     
         19 . A circuit comprising: 
 means for selecting between two inputs of a first multiplexer, the two inputs of the first multiplexer being coupled to outputs of a second multiplexer and a third multiplexer;    means for selecting between two inputs of the second multiplexer, the selecting of the second multiplexer performed when the selecting of the first multiplexer results in the first multiplexer selecting the output of the third multiplexer; and    means for selecting between two inputs of the third multiplexer, the selecting of the third multiplexer performed when the selecting of the first multiplexer results in the first multiplexer selecting the output of the second multiplexer.