US2004228346A1PendingUtilityA1

Integrated ATM/packet segmentation-and-reassembly engine for handling both packet and ATM input data and for outputting both ATM and packet data

Priority: Mar 30, 2000Filed: Jun 15, 2004Published: Nov 18, 2004
Est. expiryMar 30, 2020(expired)· nominal 20-yr term from priority
H04L 2012/5652H04L 12/5601H04L 2012/5665
49
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Claims

Abstract

An integrated ATM/packet segmentation-and-reassembly engine for handling both packet and ATM input data and outputting packets containing information from both the packet and ATM input data. The integrated ATM/packet segmentation-and-reassembly engine is also configured for receiving packets containing information destined for transmission as ATM cells and information destined for transmission as packets, perform the segregation function and segmentation function on the information destined for transmission as ATM cells in order to output both ATM cells and packets. Architecture includes the ability to output both ATM cells and packets on a single optical fiber.

Claims

exact text as granted — not AI-modified
1 . (Cancelled)  
     
     
         2 . An apparatus having a first bidirectional port, a second bidirectional port, and a third bidirectional port, the apparatus comprising: 
 a card, wherein first ATM cells formatted as cells are received onto the card via the first bidirectional port, wherein first packets formatted as packets are received onto the card via the second bidirectional port, wherein second packets formatted as packets are received onto the card via the third bidirectional port; and wherein third packets formatted as packets are received onto the card via the third bidirectional port;    a memory disposed on the card; and    a processor disposed on the card and coupled to the memory, wherein the processor executes instructions causing the apparatus to: 
 reassemble said first ATM cells into fourth packets;  
 combine said first packets and said fourth packets into a combined stream, said combined stream being output from said card via the third bidirectional port; and  
 segment said second packets into second ATM cells formatted as cells, said second ATM cells being output from said card via the first bidirectional port said third packets being output from said card via the second bidirectional port.  
   
     
     
         3 . The apparatus of  claim 2 , wherein the card has a card edge connector.  
     
     
         4 . The apparatus of  claim 2 , wherein the instructions also allow the apparatus to adjust dynamically a relative bandwidth between packet traffic passing through the second bidirectional port and ATM cell traffic passing through the first bidirectional port.  
     
     
         5 . The apparatus of  claim 4 , wherein the packet traffic passing through the second bidirectional port includes the first packets and the third packets, and wherein the ATM cell traffic passing through the first bidirectional port includes the first cells and the second cells.

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