Interconnection pattern design

Abstract

An interconnection pattern design, which has an improved reliability under mechanical shock and thermal cycling loads. A semiconductor component comprises a plurality of interconnections aligned into rows and columns to form an interconnection pattern, wherein the interconnections are aligned such that the pattern has substantially rounded or chamfered corners. The present invention provides an improved interconnection life and reliability of ball grid array packages and it is easily implemented.

1 . A semiconductor component comprising a plurality of interconnections aligned into rows and columns to form an interconnection pattern, wherein the interconnections are aligned such that the pattern has substantially rounded or chamfered corners.  
     
     
         2 . The semiconductor component as claimed in  claim 1 , wherein the interconnection pattern is formed as a ball grid array in which at least two electrically connecting joints at each corner of the array are missing.  
     
     
         3 . The semiconductor component as claimed in  claim 1 , wherein the interconnection pattern is formed as a ball grid in which at least the outermost rows and the outermost columns of the grid have less electrically connecting joints than the second outermost rows and the second outermost columns of the grid, and in which the second outermost rows and the second outermost columns of the grid have equal amount electrically connecting joints or less than the third outermost rows and the third outermost columns of the grid.  
     
     
         4 . The semiconductor component as claimed in  claim 1 , wherein the interconnection pattern is formed as a ball grid array in which at least two joints at each corner of the array are missing.  
     
     
         5 . The semiconductor component as claimed in  claim 1 , wherein the interconnection pattern is formed as a ball grid in which at least the outermost rows and the outermost columns of the grid have fewer amount of joints than the second outermost rows and the second outermost columns of the grid, and in which the second outermost rows and the second outermost columns of the grid have equal or fewer amount of joints than the third outermost rows and the third outermost columns of the grid.  
     
     
         6 . A semiconductor component as claimed in  claim 1 , wherein a plurality of bonding joints are located about the periphery of the component in an array arrangement, wherein the bonding joints are positioned in first, second and at least in one third loops, the first, second and third loops comprising respectively an outer loop, a middle loop, and an inner loop along the sides of the component, the joints in the outer loop being positioned such that the outer loop has substantially rounded or chamfered corners.  
     
     
         7 . A semiconductor device comprising at least one printed wiring board (PWB) and at least one semiconductor component bonded to the PWB, wherein interconnections formed as a pattern between the PWB and at least one component are aligned such that the pattern has substantially rounded or chamfered corners.  
     
     
         8 . A semiconductor device as claimed in  claim 7 , wherein the semiconductor device is a portable device.  
     
     
         9 . A semiconductor device as claimed in  claim 7 , wherein the interconnection pattern is formed as a ball grid array in which at least two electrically connecting joints at each corner of the array are missing.  
     
     
         10 . A semiconductor device as claimed in  claim 7 , wherein the interconnection pattern is formed as a ball grid in which at least the outermost rows and the outermost columns of the grid have fewer amount of electrically connecting joints than the second outermost rows and the second outermost columns of the grid, and in which the second outermost rows and the second outermost columns of the grid have equal or fewer amount of electrically connecting joints than the third outermost rows and the third outermost columns of the grid.  
     
     
         11 . A semiconductor device as claimed in  claim 7 , wherein a plurality of bonding joints are located about the periphery of the component in an array arrangement, wherein the bonding joints are positioned in first, second and at least one third loops, the first, second and third loops comprising respectively an outer loop, a middle loop, and an inner loop along the sides of the component, the joints in the outer loop being positioned such that the outer loop has substantially rounded or chamfered corners.  
     
     
         12 . A method for designing a semiconductor component comprising an interconnection pattern formed as a ball grid, wherein the interconnections are designed to align such that the pattern has substantially rounded or chamfered corners.  
     
     
         13 . A method as claimed in  claim 12 , wherein joint pattern is designed to a form of a ball grid array in which at least two electrically connecting joints at each corner of the array are missing.  
     
     
         14 . A method as claimed in  claim 12 , wherein the interconnection pattern is designed to a form of a ball grid in which at least the outermost rows and the outermost columns of the grid have fewer amount of electrically connecting joints than the second outermost rows and the second outermost columns of the grid, and in which the second outermost rows and the second outermost columns of the grid have fewer amount of electrically connecting joints than the third outermost rows and the third outermost columns of the grid.  
     
     
         15 . A method as claimed in  claim 12 , wherein joint pattern is designed to a form of a ball grid array in which at least two joints at each corner of the array are missing.  
     
     
         16 . A method as claimed in  claim 12 , wherein the interconnection pattern is designed to a form of a ball grid in which at least the outermost rows and the outermost columns of the grid have fewer amount of joints than the second outermost rows and the second outermost columns of the grid, and in which the second outermost rows and the second outermost columns of the grid have fewer amount of joints than the third outermost rows and the third outermost columns of the grid.  
     
     
         17 . A method as claimed in  claim 12 , wherein a plurality of bonding joints is located about the periphery of the component in an array arrangement in which at least joints of the outermost loop of the array are positioned such that the loop has substantially rounded or chamfered corners.  
     
     
         18 . A method as claimed in  claim 12 , wherein the joint pattern is designed to comprise a plurality of additional non electrically connecting joints forming at least a part of the substantially rounded or chamfered corners of the pattern.