Data pre-fetch control mechanism and method for retaining pre-fetched data after PCI cycle termination

Abstract

A data pre-fetch control mechanism of a host chipset is disclosed for fetching data from a memory subsystem of a computer system and retaining pre-fetched data based on Peripheral Component Interconnect (PCI) cycle termination. Such a data pre-fetch control mechanism comprises an interface control logic arranged to interface with a PCI bus; a data FIFO arranged to store pre-fetched data from a main memory to a requesting PCI device, via said PCI bus; and a pre-fetch control logic operatively connected to the interface control logic and the data FIFO, and arranged to control data fetch operations and retain pre-fetched data after on PCI cycle termination to optimize PCI bus operations and performances.

What is claimed is:  
     
         1 . A data pre-fetch control mechanism, comprising: 
 an interface control logic arranged to interface with a bus;    a data buffer arranged to store pre-fetched data from a main memory to a requesting bus device, via said bus; and    a pre-fetch control logic operatively connected to said interface control logic and said data buffer, and arranged to control data fetch operations and retain pre-fetched data after bus cycle termination to optimize bus operations and performances.    
     
     
         2 . The mechanism as claimed in  claim 1 , wherein said bus corresponds to a Peripheral Component Interconnect (PCI) bus, said requesting bus device corresponds to a requesting PCI master connected to said PCI bus, and said data buffer corresponds to a data first-in, first-out (FIFO) for retaining pre-fetched data from said main memory on one side of an I/O controller hub (ICH) for delivery to the requesting PCI master to another side of said ICH, via said PCI bus.  
     
     
         3 . The mechanism as claimed in  claim 1 , wherein said pre-fetch control logic is configured to make decisions about said bus cycle termination to determine if the pre-fetched data is to be flushed so as to optimize bus operations and performances.  
     
     
         4 . The mechanism as claimed in  claim 2 , wherein said pre-fetch control logic is configured to: 
 fetch data from said main memory to said data FIFO and deliver pre-fetched data stored in said data FIFO to the requesting PCI master, via said PCI bus, when a PCI read request is received from the requesting PCI master, via said interface control logic;    determine whether there is more pre-fetched data stored in said data FIFO;    if there is more pre-fetched data stored in said data FIFO, continue to deliver pre-fetched data to the requesting PCI master, via said PCI bus, and fetch data ahead from the main memory until there is no more pre-fetched data stored in said data FIFO;    if there is no more pre-fetched data stored in said data FIFO, disconnect the transaction;    determine whether the requesting PCI master requests more data from said main memory;    if the requesting PCI master requests more data from said main memory, determine whether the requesting PCI master returns a next address for a memory read;    if the requesting PCI master returns a next address for said memory read, return to fetch data from said main memory to said data FIFO and deliver the pre-fetched data to the requesting PCI master, via the PCI bus;    if the requesting PCI master does not request more data from said main memory, flush any additional pre-fetched data from said data FIFO; and    if the requesting PCI master does not return a next address for said memory read, flush any additional pre-fetched data from said data FIFO based on predetermined conditions.    
     
     
         5 . The mechanism as claimed in  claim 2 , wherein said pre-fetch control logic is configured to: 
 fetch data from said main memory to said data FIFO and deliver pre-fetched data stored in said data FIFO to a requesting PCI master, via said PCI bus, when a PCI read request is received from the requesting PCI master, via said interface control logic;    determine whether there is more pre-fetched data stored in said data FIFO;    if there is no more pre-fetched data stored in said data FIFO, disconnect the transaction and determine whether said data FIFO must be flushed for other pending transactions;    if there is more pre-fetched data stored in said data FIFO, determine whether the requesting PCI master requests more data from said main memory;    if the requesting PCI master requests more data from the main memory, return to fetch data from said main memory to said data FIFO and deliver the pre-fetched data to the requesting PCI master, via said PCI bus,    if the requesting PCI master does not request more data from said main memory, proceed to determine whether other transaction is pending;    if no other transaction is pending, proceed to determine whether there is more pre-fetched data stored in said data FIFO; and    alternatively, if there is another transaction pending, flush any additional pre-fetched data from said data FIFO.    
     
     
         6 . The mechanism as claimed in  claim 2 , wherein said pre-fetch control logic is further implemented to receive variables of said PCI read request, a bus frequency, and a bus data width signal from the requesting PCI master, and to generate fetch sizes of data to be fetched from the main memory to the requesting PCI master as a function of said PCI read request, said bus frequency, and said bus data width signal.  
     
     
         7 . The mechanism as claimed in  claim 6 , wherein said PCI read request corresponds to one of a memory read command, a memory read line command, and a memory read multiple command for reading different amount of data from said main memory during a read cycle.  
     
     
         8 . The mechanism as claimed in  claim 6 , wherein said bus frequency corresponds to one of 33 MHz and 66 MHz, based upon assertion of 66MHz_ENABLE pin from the requesting PCI master connected to said PCI bus, and said bus data width signal corresponds to one of 32 bits and 64 bits, based upon assertion of REQ64# pin from the requesting PCI master connected to said PCI bus.  
     
     
         9 . A computer system, comprising: 
 a memory subsystem;    a host chipset connected to said memory subsystem; and    a bus device connected to said host chipset, via a bus;    said host chipset comprising a data pre-fetch control mechanism for fetching data from said memory subsystem for said bus device and retaining pre-fetched data based on bus cycle termination, said data pre-fetch control mechanism comprising: 
 an interface control logic arranged to interface with said bus;  
 a data FIFO arranged to store pre-fetched data from said memory subsystem to a requesting bus device, via said bus; and  
 a pre-fetch control logic operatively connected to said interface control logic and said data FIFO, and arranged to control data fetch operations and retain pre-fetched data after said bus cycle termination to optimize bus operations and performances.  
   
     
     
         10 . The computer system as claimed in  claim 9 , wherein said bus corresponds to a Peripheral Component Interconnect (PCI) bus, said requesting bus device corresponds to a requesting PCI master connected to said PCI bus.  
     
     
         11 . The computer system as claimed in  claim 10 , wherein said host chipset corresponds to one of an I/O Controller Hub (ICH) and a Peripheral Component Interconnect (PCI) 64-bit hub.  
     
     
         12 . The computer system as claimed in  claim 9 , wherein said pre-fetch control logic is configured to make decisions about said bus cycle termination to determine if the pre-fetched data is to be flushed so as to optimize bus operations and performances.  
     
     
         13 . The computer system as claimed in  claim 10 , wherein said pre-fetch control logic is configured to: 
 fetch data from said memory subsystem to said data FIFO and deliver pre-fetched data stored in said data FIFO to the requesting PCI master, via said PCI bus, when a PCI read request is received from the requesting PCI master, via said interface control logic;    determine whether there is more pre-fetched data stored in said data FIFO;    if there is more pre-fetched data stored in said data FIFO, continue to deliver pre-fetched data to the requesting PCI master, via said PCI bus, and fetch data ahead from said memory subsystem until there is no more pre-fetched data stored in said data FIFO;    if there is no more pre-fetched data stored in said data FIFO, disconnect the transaction;    determine whether the requesting PCI master requests more data from said memory subsystem;    if the requesting PCI master requests more data from said memory subsystem, determine whether the requesting PCI master returns a next address for a memory read;    if the requesting PCI master returns a next address for said memory read, return to fetch data from said memory subsystem to said data FIFO and deliver the pre-fetched data to the requesting PCI master, via the PCI bus;    if the requesting PCI master does not request more data from said memory subsystem, flush any additional pre-fetched data from said data FIFO; and    if the requesting PCI master does not return a next address for said memory read, flush any additional pre-fetched data from said data FIFO based on predetermined conditions.    
     
     
         14 . The computer system as claimed in  claim 10 , wherein said pre-fetch control logic is configured to: 
 fetch data from said memory subsystem to said data FIFO and deliver pre-fetched data stored in said data FIFO to a requesting PCI master, via said PCI bus, when a PCI read request is received from the requesting PCI master, via said interface control logic;    determine whether there is more pre-fetched data stored in said data FIFO;    if there is no more pre-fetched data stored in said data FIFO, disconnect the transaction and determine whether said data FIFO must be flushed for other pending transactions;    if there is more pre-fetched data stored in said data FIFO, determine whether the requesting PCI master requests more data from said memory subsystem;    if the requesting PCI master requests more data from said memory subsystem, return to fetch data from said memory subsystem to said data FIFO and deliver the pre-fetched data to the requesting PCI master, via said PCI bus,    if the requesting PCI master does not request more data from said memory subsystem, proceed to determine whether other transaction is pending;    if no other transaction is pending, proceed to determine whether there is more pre-fetched data stored in said data FIFO; and    alternatively, if there is another transaction pending, flush any additional pre-fetched an data from said data FIFO.    
     
     
         15 . The computer system as claimed in  claim 10 , wherein said pre-fetch control logic is further implemented to receive variables of said PCI read request, a bus frequency, and a bus data width signal from the requesting PCI master, and to generate fetch sizes of data to be fetched from the main memory to the requesting PCI master as a function of said read command, said bus frequency, and said bus data width signal.  
     
     
         16 . The computer system as claimed in  claim 15 , wherein said PCI read request corresponds to one of a memory read command, a memory read line command, and a memory read multiple command for reading different amount of data from the main memory during a read cycle.  
     
     
         17 . The computer system as claimed in  claim 16 , wherein said bus frequency corresponds to one of 33 MHz and 66 MHz, based upon assertion of 66MHz_ENABLE pin from the requesting PCI master connected to said PCI bus, and said bus data width signal corresponds to one of 32 bits and 64 bits, based upon assertion of REQ64# pin from the requesting PCI master connected to said PCI bus.  
     
     
         18 . A data pre-fetch method comprising: 
 receiving a PCI read request from a requesting PCI master, via a PCI bus;    in response to said PCI read request, fetching data from a memory subsystem to a data FIFO and delivering pre-fetched data stored in said data FIFO to the requesting PCI master, via said PCI bus;    determining whether there is more pre-fetched data stored in said data FIFO;    if there is more pre-fetched data stored in said data FIFO, continuing to deliver pre-fetched data to the requesting PCI master, via said PCI bus, and fetching data ahead from said memory subsystem until there is no more pre-fetched data stored in said data FIFO;    if there is no more pre-fetched data stored in said data FIFO, disconnecting the transaction;    determining whether the requesting PCI master requests more data from said memory subsystem;    if the requesting PCI master requests more data from said memory subsystem, determining whether the requesting PCI master returns a next address for a memory read;    if the requesting PCI master returns a next address for said memory read, returning to fetch data from said memory subsystem to said data FIFO and deliver the pre-fetched data to the requesting PCI master, via the PCI bus;    if the requesting PCI master does not request more data from said memory subsystem, flushing any additional pre-fetched data from said data FIFO; and    if the requesting PCI master does not return a next address for said memory read, flushing any additional pre-fetched data from said data FIFO based on predetermined conditions.    
     
     
         19 . A data pre-fetch method comprising: 
 receiving a PCI read request from a requesting PCI master, via a PCI bus;    in response to said PCI read request, fetching data from a memory subsystem to a data FIFO and delivering pre-fetched data stored in said data FIFO to the requesting PCI master, via said PCI bus;    determining whether there is more pre-fetched data stored in said data FIFO;    if there is no more pre-fetched data stored in said data FIFO, disconnecting the transaction and determining whether said data FIFO must be flushed for other pending transactions;    if there is more pre-fetched data stored in said data FIFO, determining whether the requesting PCI master requests more data from said memory subsystem;    if the requesting PCI master requests more data from said memory subsystem, returning to fetch data from said memory subsystem to said data FIFO and deliver the pre-fetched data to the requesting PCI master, via said PCI bus,    if the requesting PCI master does not request more data from said memory subsystem, proceeding to determine whether other transaction is pending;    if no other transaction is pending, proceeding to determine whether there is more pre-fetched data stored in said data FIFO; and    alternatively, if there is another transaction pending, flushing any additional pre-fetched data from said data FIFO based on predetermined conditions.    
     
     
         20 . The method as claimed in  claim 19 , wherein said PCI read request corresponds to one of a memory read command, a memory read line command, and a memory read multiple command for reading different amount of data from said memory subsystem during a read cycle.