Functional pathway configuration at a system/IC interface

Abstract

The present invention relates generally to functional pathway configurations at the interfaces between integrated circuits (ICs) and the circuit assemblies with which the ICs communicate. More particularly, the present invention relates generally to the functional pathway configuration at the interface between a semiconductor chip including an IC (e.g., computer chips like microcontrollers and microprocessors) and the circuitry of a system including the chip. Even more particularly, the present invention relates to a 20-pin microcontroller functional pathway configuration for the interface between the microcontroller and a system in which the microcontroller is embedded.

What is claimed is:  
     
         1 . A microcontroller having a functional pathway configuration for the interface between the microcontroller and a system with which the microcontroller communicates, as follows:  
       
         
           
           
               
               
           
         
       
     
     
         2 . A system/IC interface forming a functional pathway configuration including at least two input/output ports comprising: 
 a first port including a first set of eight pins P 1 , P 2 , P 3  . . . P 8 , each of the eight pins of the first set having dedicated functions as follows:                                                    PIN   DIRECTION   DEDICATED FUNCTION(S)                   P1   I   RA0/AN0/OPA+         P2   I   RA1/AN1/OPA−         P3   I/O   RA2/AN2/VREF2         P4   I/O   RA3/AN3/VREF1         P5   I/O   RA4/T0CKI         P6   I   RA5/{overscore (MCLR)}/VPP         P7   I/O   RA6/OSC2/CLKOUT         P8   I/O   RA7/OSC1/CLKIN/T1CKI                                                      and    a second port including a second set of eight pins P 9 , P 10 , P 11  . . . P 16 , each of the eight pins of the second set having dedicated functions as follows:                                                    PIN   DIRECTION   DEDICATED FUNCTION(S)                   P9    I/O   RB0/INT/AN4/VREF         P10   I/O   RB1/AN5/VDAC         P11   I/O   RB2/AN6         P12   I/O   RB3/AN7/OPA         P13   I/O   RB4         P14   I/O   RB5         P15   I/O   RB6/C1/PSMC1A         P16   I/O   RB7/C2/PSMC1B/{overscore (T1G)}