Process for manufacturing semiconductor wafer and semiconductor wafer

Abstract

The present invention provides a process for manufacturing a semiconductor wafer capable of effectively reducing unevenness having a wavelength of 0.5 mm or more which remains on a surface of the semiconductor wafer after a first polishing step and improving flatness thereof and a semiconductor wafer manufactured by the manufacturing process. The manufacturing process comprises: plural polishing steps including a first polishing step and a final polishing step; and a corrective polishing step performed after the first polishing step using a polishing cloth harder than that used in the first polishing step.

1 . A process for manufacturing a semiconductor wafer comprising: plural polishing steps including a first polishing step and a final polishing step; and a corrective polishing step performed after the first polishing step using a polishing cloth harder than that used in the first polishing step.  
     
     
         2 . A process according to  claim 1 , wherein hardness of the polishing cloth used in the first polishing step is in the range of from 73 to 86 in Asker-C scale and hardness of the polishing cloth used in the corrective polishing cloth is in the range of from 80 to 98 in Asker-C scale.  
     
     
         3 . A process according to  claim 1  or  2 , wherein unevenness having a wavelength of 0.5 mm or more on a surface of the semiconductor wafer remaining after the first polishing step is reduced in the corrective polishing step.  
     
     
         4 . A process according to any of  claims 1  to  3 , wherein the polishing cloth used in the corrective polishing step is a high hardness polishing cloth prepared by impregnating non-woven fabrics with urethane resins or a polishing cloth of chemical reaction foamed materials.  
     
     
         5 . A process according to any of  claims 1  to  4 , wherein the plural polishing steps include the first polishing step, a second polishing step and the final polishing step, the corrective polishing step being added after the first polishing step.  
     
     
         6 . A semiconductor wafer, wherein when a semiconductor wafer surface is evaluated in an area 0.5 mm square, an occupancy rate of the area where a P-V value is 15 nm or more in the semiconductor wafer surface is less than 0.01%.  
     
     
         7 . A semiconductor wafer according to  claim 6 , wherein when a semiconductor wafer surface is evaluated in an area 2.0 mm square, an occupancy rate of the area where a P-V value is 20 nm or more in the semiconductor wafer surface is less than 0.15%.  
     
     
         8 . A semiconductor wafer according to  claim 6  or  7 , wherein when a semiconductor wafer surface is evaluated in an area 10.0 mm square, an occupancy rate of the area where a P-V value is 50 nm or more in the semiconductor wafer surface is less than 0.15%.