Semiconductor package including a double-faced semiconductor chip having integrated circuitry on both sides thereof and a method of fabricating the semiconductor package
Abstract
A semiconductor package including a double-faced semiconductor chip having integrated circuitry on both sides thereof, and a method of fabricating the same is provided, wherein the semiconductor package includes the semiconductor chip; a lead-on-chip (LOC)-type substrate, having metal patterns on both sides, bonded with the first side of the semiconductor chip; first wires for connecting the first side of the semiconductor chip to the second side of the LOC-type substrate; second wires for connecting the second side of the semiconductor chip to the first side of the LOC-type substrate; a first sealing material for covering the semiconductor chip, the first wires, and the second side of the LOC-type substrate; a second sealing material for covering the semiconductor chip, the second wires, and the first side of the LOC-type substrate; and solder balls attached to the second side of the LOC-type substrate.
Claims
exact text as granted — not AI-modified1 . A semiconductor package including a double-faced semiconductor chip having a first and a second side, the semiconductor package comprising:
a semiconductor chip having integrated circuitry on the first and second sides thereof; a lead-on-chip (LOC)-type substrate, having a first and a second side and a metal pattern on both sides thereof, which is bonded with the first side of the semiconductor chip with an adhesive; a plurality of first wires, each for connecting a bonding pad on the first side of the semiconductor chip to the metal pattern on the second side of the LOC-type substrate; a plurality of second wires, each for connecting a bonding pad on the second side of the semiconductor chip to the metal pattern on the first side of the LOC-type substrate; a first sealing material for covering a portion of the first side of the exposed semiconductor chip, the plurality of first wires, and a portion of the second side of the LOC-type substrate on a center of an upper portion of the LOC-type substrate; a second sealing material for covering the semiconductor chip, the plurality of second wires, and the first side of the LOC-type substrate on a lower portion of the LOC-type substrate; and a plurality of solder balls attached to the second side of the LOC-type substrate.
2 . The semiconductor package as claimed in claim 1 , wherein the bonding pad is formed at a center of the integrated circuitry formed on the first side of the semiconductor chip.
3 . The semiconductor package as claimed in claim 1 , wherein the bonding pad is formed at an edge of the integrated circuitry formed on the second side of the semiconductor chip.
4 . The semiconductor package as claimed in claim 1 , wherein the LOC-type substrate is formed of polyimide tape.
5 . The semiconductor package as claimed in claim 1 , wherein the integrated circuitry formed on the first side of the semiconductor chip has the same function as the integrated circuitry formed on the second side of the semiconductor chip.
6 . The semiconductor package as claimed in claim 1 , wherein the integrated circuitry formed on the first side of the semiconductor chip has a different function from the integrated circuitry formed on the second side of the semiconductor chip.
7 . The semiconductor package as claimed in claim 1 , wherein the adhesive that bonds the semiconductor chip with the LOC-type substrate is formed of elastomer.
8 . The semiconductor package as claimed in claim 1 , wherein the first sealing material is liquid encapsulant.
9 . The semiconductor package as claimed in claim 1 , wherein the second sealing material is epoxy mold compound.
10 . The semiconductor package as claimed in claim 1 , wherein each of the metal patterns on the first and second sides of the LOC-type substrate is a bonding finger.Join the waitlist — get patent alerts
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