Parallel pipelined merge engines

Abstract

An image generator is organized into a plurality of rendering engines, each of which renders an image of a part scene and provides the part image to a merge engine associated with that rendering engine. The image is a part image in that it usually contains less than all of the objects in the image to be rendered. The merge engine merges the part image from its associated rendering engine with the part image provided by a prior merge engine and provides the merged part image to a next merge engine. One or more merge engines are designated the output merge engines and these output merge engines output a merged part image that is (a portion of) the ultimate output of the image generator, the full rendered image. Each merge engine performs its merge process on the pixels it has from its rendering engine and from its prior neighbor merge engine, in a pipelined manner and without necessarily waiting for all of the pixels of the part image or the merged part image.

What is claimed:  
     
         1 . A system for generating images comprising: 
 a pixel bus;    a host bus;    a plurality of merge engines, each merge engine comprising: 
 a pixel bus interface circuit configured to send and receive pixel data and control messages over the pixel bus between merge engines;  
 a part image bus configured to communicate with a render engine associated the merge engine; and  
 a host interface configured to send and receive pixel data and control messages over the host bus between the merge engine and a host system.  
   
     
     
         2 . The system of  claim 1  wherein the control messages over the host bus between the merge engine and a host system comprise synchronization messages.  
     
     
         3 . The system of  claim 1  wherein the control messages over the host bus between the merge engine and a host system comprise initialization messages.  
     
     
         4 . The system of  claim 1  wherein the merge engine further comprises a plurality of control registers.  
     
     
         5 . The system of  claim 4  wherein the control messages over the host bus between the merge engine and a host system comprise control data to be written to the control registers.  
     
     
         6 . The system of  claim 4  wherein the control messages over the pixel bus between merge engines comprise control data to be written to the control registers.  
     
     
         7 . The system of  claim 4  wherein the control registers comprise a first plurality of control registers and a second identical plurality of control registers.  
     
     
         8 . The system of  claim 7  wherein only the first plurality of registers can be modified by messages on the pixel bus.  
     
     
         9 . A graphics merge engine comprising: 
 a pixel bus interface circuit configured to send and receive pixel data and control messages over a pixel bus between merge engines;    a part image bus configured to communicate with a render engine associated the merge engine;    a host interface configured to send and receive pixel data and control messages over a host bus between the merge engine and a host system; and    a pixel data compare circuit in communication with the pixel bus interface, part image bus, and host interface.    
     
     
         10 . The graphics merge engine of  claim 9  further comprising a plurality of control registers.  
     
     
         11 . The graphics merge engine of  claim 10  wherein the plurality of control registers comprises a first plurality and a second identical plurality of control registers.  
     
     
         12 . The graphics merge engine of  claim 11  wherein only the first plurality of control registers can be modified by messages on the pixel bus.  
     
     
         13 . A graphics processing system comprising: 
 a host processor;    a rendering engine;    a graphics memory in communication with the rendering engine;    a merge processor in communication with the graphics memory, the merge processor comprising: 
 a pixel bus interface circuit configured to send and receive pixel data and control messages over the pixel bus between other merge processors and workstations;  
 a host interface configured to send and receive pixel data and control messages over the host bus between the merge processor and the host processor; and  
 a pixel merge circuit.  
   
     
     
         14 . The system of  claim 13  wherein the control messages over the host bus between the merge processor and the host processor comprise synchronization messages.  
     
     
         15 . The system of  claim 13  wherein the control messages over the host bus between the merge processor and the host processor comprise initialization messages.  
     
     
         16 . The system of  claim 13  wherein the merge processor further comprises a plurality of control registers.  
     
     
         17 . The system of  claim 16  wherein the control messages over the host bus between the merge processor and the host processor comprise control data to be written to the control registers.  
     
     
         18 . The system of  claim 16  wherein the control messages over the pixel bus between merge processors comprise control data to be written to the control registers.  
     
     
         19 . The system of  claim 16  wherein the control registers comprise a first plurality of control registers and a second identical plurality of control registers.  
     
     
         20 . The system of  claim 19  wherein only the first plurality of registers can be modified by the messages on the pixel bus.  
     
     
         21 . A graphics processing system comprising: 
 a pixel bus for communicating data comprising pixel information;    a plurality of merge processors for merging pixel information received from at least one neighbor processor;    a plurality of rendering processors in communication with at least one merge processor and for rendering pixel information; and    a switch network for assigning and reassigning which processors are input neighbors and which processors are output neighbors.    
     
     
         22 . The system of  claim 21  wherein at least one merge processor comprises an identifying address on the pixel bus and wherein the identifying address is modifiable by the switch network.  
     
     
         23 . The system of  claim 21  wherein each merge processor comprises an identifying address on the pixel bus and wherein the identifying address is modifiable by the switch network to define which processors are input neighbors and which processors are output neighbors.  
     
     
         24 . A graphics processing system comprising: 
 a pixel bus for communicating data comprising pixel information;    a plurality of merge processors for merging pixel information received from at least one neighbor processor, the plurality of merge processors forming a first state of input neighbor and output neighbor associations for a first image and a second state of input neighbor and output neighbor associations for a second image;    a plurality of rendering processors in communication with at least one merge processor and for rendering pixel information; and    a switch network for changing between the first state of input neighbor and output neighbor associations for the first image and the second state of input neighbor and output neighbor associations for the second image.    
     
     
         25 . The system of  claim 24  wherein the first state comprises a pipeline configuration between a merge processor, its input neighbor processor, and its output neighbor processor.  
     
     
         26 . The system of  claim 24  wherein the first state of input neighbor and output neighbor associations comprises a first processor and a second processor and wherein the first processor is an input processor to the second processor and wherein the second state of input neighbor and output neighbor associations comprises the first processor being an output neighbor to the second processor.  
     
     
         27 . The system of  claim 24  wherein the first state of input neighbor and output neighbor associations comprises a first processor and a second processor and wherein the first processor is an input neighbor to the second processor and wherein the second state of input neighbor and output neighbor associations comprises the first processor not being an input or output neighbor to the second processor.  
     
     
         28 . The system of  claim 24  wherein at least one merge processor comprises an identifying address on the pixel bus.  
     
     
         29 . The system of  claim 24  wherein each merge processor comprises an identifying address on the pixel bus and wherein the identifying address is modifiable by the switch network to define which processors are input neighbors and which processors are output neighbors.  
     
     
         30 . The system of  claim 24  wherein each merge processor comprises at least one configurable neighbor processor input that can receive pixel information from any one or more definable input neighbor processors and at least one dynamically configurable neighbor processor output that can output pixel information to any one or more definable output neighbor processors.  
     
     
         31 . A system for generating images comprising: 
 a plurality of merge engines comprising at least one merge engine having a plurality of configuration registers that identify a plurality of operating modes of the merge engine;    a host in communication with at least the at least one merge engine and arranged to write data to the configuration registers to configure the merge engine to operate in at least a first mode of image analysis.    
     
     
         32 . The system of  claim 31  wherein the host further comprises logic for writing data to the configuration registers to configure the merge engine to operate in at least a second mode of image analysis.  
     
     
         33 . The system of  claim 31  wherein the first mode of image analysis comprises a pixel depth comparison mode of operation.  
     
     
         34 . The system of  claim 31  wherein the first mode of image analysis comprises a pixel blending mode of operation.  
     
     
         35 . The system of  claim 31  wherein the first mode of image analysis comprises a pixel data pass-through mode of operation.  
     
     
         36 . A network comprising: 
 a plurality of workstations in communication with each other, at least one work station comprising: 
 a memory;  
 an image rendering engine;  
 an image merge engine in communication with the rendering engine and comprising: 
 an input neighbor merge engine data bus;  
 an output neighbor merge engine data bus; and  
 a plurality of registers that define a first state of input neighbor merge engine and output neighbor merge engine associations and wherein the plurality of registers are modifiable to define a second state of input neighbor merge engine and output neighbor merge engine associations different from the first.  
 
   
     
     
         37 . The network of  claim 36  wherein an image merge engine associated with a first workstation comprises an input neighbor merge engine to an image merge engine associated with a second workstation.  
     
     
         38 . The network of  claim 36  wherein an image merge engine associated with a first workstation comprises an output neighbor merge engine to an image merge engine associated with a second workstation.