Interpolator circuit

Abstract

An improved interpolator includes a replica delay line and an interpolated delay edge generator. The replica delay line provides two replica delay edges to the interpolated delay edge generator. The interpolated delay edge generator selectively generates an interpolated delay edge while maintaining a substantially constant capacitive loading on the two replica delay edges. The replica delay line may comprise a delay cell of four current-starved inverter delay stages or four capacitor-loaded inverter delay stages.

1 . An interpolator circuit comprising: 
 a replica delay line to receive an input signal and to provide a first replica delay edge and a second replica delay edge based, at least in part, on the input signal; and    an interpolated delay edge generator to receive the first replica delay edge and the second replica delay edge and to provide an interpolated delay edge selectively having a value between the first replica delay edge the second replica delay edge, wherein a capacitive loading of the first replica delay edge and the second replica delay edge is substantially the same for each selected value of the interpolated delay edge.    
     
     
         2 . The interpolator circuit of  claim 1 , wherein the interpolated delay edge generator comprises: 
 a pass-gate voltage divider having as an input the first replica delay edge and the second replica delay edge and having as an output the interpolated delay edge, the pass-gate voltage divider selectable between an on condition and an off condition; and    a replica pass-gate voltage divider having as an input the first replica delay edge and the second replica delay edge and selectable between an on condition and an off condition, wherein the replica pass-gate voltage divider is in the on condition when the pass-gate voltage divider is in the off condition to provide a substantially constant capacitive loading on the first replica delay edge and the second replica delay edge.    
     
     
         3 . The interpolator circuit of  claim 1 , wherein the interpolated delay edge generator comprises: 
 two or more voltage divider stages, each voltage divider stage including 
 a pass-gate voltage divider having as an input the first replica delay edge and the second replica delay edge and having as an output the interpolated delay edge, the pass-gate voltage divider selectable between an on condition and an off condition; and  
 a replica pass-gate voltage divider having as an input the first replica delay edge and the second replica delay edge and selectable between an on condition and an off condition, wherein the replica pass-gate voltage divider is in the on condition when the pass-gate voltage divider is in the off condition to provide a substantially constant capacitive loading on the first replica delay edge and the second replica delay edge,  
 wherein an output of each voltage divider stage provides an input for a succeeding voltage divider stage; and  
   an inverter in electrical communication with an output of a final voltage divider stage to provide the interpolated delay edge, wherein a value of the interpolated delay edge is based, at least in part, on which of the two or more voltage divider stages is in the on condition.    
     
     
         4 . The interpolator circuit of  claim 1 , wherein the replica delay line comprises a delay cell of four current-starved inverter delay stages.  
     
     
         5 . The interpolator circuit of  claim 1 , further comprising an analog bias generator.  
     
     
         6 . The interpolator circuit of  claim 1 , wherein the replica delay line comprises a delay cell of four capacitor-loaded inverter delay stages.  
     
     
         7 . An interpolator circuit comprising: 
 a replica delay line to receive an input signal and to provide a first replica delay edge and a second replica delay edge, the replica delay line including four voltage-controlled delay stages, wherein an output of each voltage-controlled delay stages provides an input to a succeeding voltage-controlled delay stage; and    an interpolated delay edge generator to receive the first replica delay edge and the second replica delay edge and to provide an interpolated delay edge selectively having a value between the first replica delay edge the second replica delay edge.    
     
     
         8 . The interpolator circuit of  claim 7 , wherein the replica delay line further comprises: 
 an input buffer to receive a delay edge as an input and to provide the delay edge to a first voltage-controlled delay stage; and    an output buffer to receive an output of a last voltage-controlled delay stage.    
     
     
         9 . The interpolator circuit of  claim 7  wherein, 
 the input buffer is a voltage-controlled delay stage; and  
 the output buffer is a voltage-controlled delay stage.  
 
     
     
         10 . The interpolator circuit of  claim 7 , wherein the four voltage-controlled delay stages of the delay line comprise four current-starved inverter delay stages and an output of each current-starved inverter delay stage provides an input to a succeeding current-starved inverter delay stage.  
     
     
         11 . The interpolator circuit of  claim 7 , wherein the four voltage-controlled delay stages of the delay line comprise four capacitor-loaded delay stages and an output of each capacitor-loaded delay stage provides an input to a succeeding capacitor-loaded stage.  
     
     
         12 . A delay-locked loop circuit comprising: 
 a phase detector to detect a phase difference between a reference signal and an interpolated delay edge and to generate a bias signal having a value that is proportional to the phase difference;    a delay line to receive as an input the reference signal and the bias signal and to provide one of a plurality of delay edges as an output; and    an interpolator to receive a delay edge from the delay line and to generate a first replica delay edge and a second replica delay edge and to provide an interpolated delay edge selectively having a value between the first replica delay edge and the second replica delay edge to the phase detector, wherein a capacitive loading of the first replica delay edge and the second replica delay edge is substantially the same for each selected value of the interpolated delay edge.    
     
     
         13 . The delay-locked loop circuit of  claim 12 , wherein the interpolator comprises: 
 a replica delay line having as an input the delay edge provided by the delay line and having as an output the first replica delay edge and the second replica delay edge; and    an interpolated delay edge generator to receive as an input the first replica delay edge and the second replica delay edge and to selectively generate an interpolated delay edge having a value between the first replica delay edge and the second replica delay edge, wherein a capacitive loading of the first replica delay edge and the second replica delay edge is substantially the same for each selected value of the interpolated delay edge.    
     
     
         14 . The delay-locked loop circuit of  claim 13 , wherein the interpolated delay edge generator comprises: 
 a pass-gate voltage divider having as an input the first replica delay edge and the second replica delay edge and having as an output the interpolated delay edge, the pass-gate voltage divider selectable between an on condition and an off condition; and    a replica pass-gate voltage divider selectable between an on condition and an off condition, wherein the replica pass-gate voltage divider is in the on condition when the pass-gate voltage divider is in the off condition to provide a substantially constant capacitive loading on the first replica delay edge and the second replica delay edge.    
     
     
         15 . The delay-locked loop circuit of  claim 13 , wherein the replica delay line comprises four current-starved inverter delay stages.  
     
     
         16 . The delay-locked loop circuit of  claim 13 , wherein the replica delay line comprises four capacitor-loaded replica delay stages.  
     
     
         17 . A delay-locked loop circuit comprising: 
 a phase detector to detect a phase difference between a reference signal and an interpolated delay edge and to provide an output signal that is indicative of the phase difference;    a delay line to receive as an input the reference signal and a bias signal and to provide one of a plurality of delay edges as an output; and    an interpolator to selectively provide an interpolated delay edge to the phase detector, the interpolator including a replica delay line to receive a delay edge from the delay line and to provide a first replica delay edge and a second replica delay edge for interpolation, the delay line having four voltage-controlled delay stages, wherein an output of each voltage-controlled delay stage provides an input to a succeeding voltage-controlled delay stage.    
     
     
         18 . The delay-locked loop circuit of  claim 17 , wherein the four voltage-controlled delay stages of the delay line comprise four current-starved inverter delay stages and an output of each current-starved inverter delay stage provides an input to a succeeding current-starved inverter delay stage.  
     
     
         19 . The delay-locked loop circuit of  claim 17 , wherein the four voltage-controlled delay stages of the delay line comprise four capacitor-loaded delay stages and an output of each capacitor-loaded delay stage provides an input to a succeeding capacitor-loaded delay stage.  
     
     
         20 . A system comprising: 
 a signal source to provide a data signal;    a latch in electrical communication with the signal source to receive the data signal; and    a delay-locked loop circuit (DLL) in electrical communication with the latch to provide an adjusted strobe signal, the DLL including an interpolator circuit having 
 a replica delay line to receive an input signal and to provide a first replica delay edge and a second replica delay edge based, at least in part, on the input signal and  
   an interpolated delay edge generator to receive the first replica delay edge and the second replica delay edge and to provide an interpolated delay edge selectively having a value between the first replica delay edge the second replica delay edge, wherein a capacitive loading of the first replica delay edge and the second replica delay edge is substantially the same for each selected value of the interpolated delay edge.    
     
     
         21 . The system of  claim 20 , wherein the interpolated delay edge generator comprises: 
 a pass-gate voltage divider having as an input the first replica delay edge and the second replica delay edge and having as an output the interpolated delay edge, the pass-gate voltage divider selectable between an on condition and an off condition; and    a replica pass-gate voltage divider having as an input the first replica delay edge and the second replica delay edge and selectable between an on condition and an off condition, wherein the replica pass-gate voltage divider is in the on condition when the pass-gate voltage divider is in the off condition to provide a substantially constant capacitive loading on the first replica delay edge and the second replica delay edge.    
     
     
         22 . The system of  claim 21 , wherein the delay line comprises four voltage-controlled delay stages, wherein an output of each voltage-controlled delay stage provides an input to a succeeding voltage-controlled delay stage.  
     
     
         23 . The system of  claim 22 , wherein the four voltage-controlled delay stages comprise four current-starved inverter delay stages.  
     
     
         24 . The system of  claim 22 , wherein the four voltage-controlled delay stages comprise four capacitor-loaded inverter delay stages.  
     
     
         25 . A system comprising: 
 a phase detector to detect a phase difference between a reference signal and an interpolated delay edge and to generate an output signal to represent the phase difference between the reference signal and the interpolated delay edge;    a delay line to receive as an input the reference signal and a voltage-controlled bias signal based, at least in part on the output signal of the phase detector, the delay line including a plurality of capacitor-loaded delay stages; and    an interpolator to receive a delay edge from the delay line and to generate a first replica delay edge and a second replica delay edge and to provide an interpolated delay edge selectively having a value between the first replica delay edge and the second replica delay edge, wherein a capacitive loading of the first replica delay edge and the second replica delay edge is substantially the same for each selected value of the interpolated delay edge.    
     
     
         26 . The system of  claim 25 , wherein the interpolator comprises: 
 a replica delay line having as an input the delay edge provided the delay line and having as an output the first replica delay edge and the second replica delay edge; and    an interpolated delay edge generator to receive as an input the first replica delay edge and the second replica delay edge and to selectively generate an interpolated delay edge having a value between the first replica delay edge and the second replica delay edge, wherein a capacitive loading of the first replica delay edge and the second replica delay edge is substantially the same for each selected value of the interpolated delay edge.    
     
     
         27 . The system of  claim 26 , wherein the interpolated delay edge generator comprises: 
 a pass-gate voltage divider having as an input the first replica delay edge and the second replica delay edge and having as an output the interpolated delay edge, the pass-gate voltage divider selectable between an on condition and an off condition; and    a replica pass-gate voltage divider selectable between an on condition and an off condition, wherein the replica pass-gate voltage divider is in the on condition when the pass-gate voltage divider is in the off condition to provide a substantially constant capacitive loading on the first replica delay edge and the second replica delay edge.    
     
     
         28 . A method comprising: 
 receiving a delay edge;    generating a first replica delay edge and a second replica delay edge based, at least in part, on the received delay edge; and    providing an interpolated delay edge selectively having a value between the first replica delay edge and the second replica delay edge, wherein a capacitive loading of the first replica delay edge and the second replica delay edge is substantially the same for each selected value of the interpolated delay edge.    
     
     
         29 . The method of  claim 28 , wherein generating the second replica delay edge comprises delaying the received delay edge by a period of time to produce the second replica delay edge.  
     
     
         30 . The method of  claim 29 , wherein the first replica delay edge is the received delay edge.