Dual damascene pattern liner

Abstract

An embodiment of the invention is a dual damascene layer 13 of an integrated circuit 2 containing a dual damascene pattern liner 21 . Another embodiment of the invention is a method of manufacturing dual damascene layer 13 where a dual damascene pattern liner 21 is formed over a cap layer 25 and within via holes. Yet another embodiment of the invention is a method of manufacturing dual damascene layer 13 where a dual damascene pattern liner 21 is formed over a cap layer 25 and within trench spaces.

1 . An integrated circuit comprising: 
 a semiconductor substrate;    a front-end structure coupled to said semiconductor substrate;    a single damascene layer coupled to said front-end structure;    a dual damascene layer coupled to said single damascene layer, said dual damascene layer comprising trenches and vias within a dielectric material; and    a dual damascene pattern liner coupled at least partially between said vias and said dielectric material but not between said trenches and said dielectric material.    
     
     
         2 . The integrated circuit of  claim 1  wherein said dielectric material comprises low-k material.  
     
     
         3 . The integrated circuit of  claim 2  wherein said low-k material comprises OSG.  
     
     
         4 . The integrated circuit of  claim 1  wherein said dual damascene pattern liner comprises a refractory metal.  
     
     
         5 . The intergrated circuit of  claim 4  wherein said refractory metal comprises TiN.  
     
     
         6 . The integrated circuit of  claim 1  wherein said dual damascene pattern liner comprises a dielectric film.  
     
     
         7 . The integrated circuit of  claim 6  wherein said dielectric film is SiN.  
     
     
         8 . The intergrated circuit of  claim 1  wherein said dual damascene pattern liner fully covers a surface of said vias.  
     
     
         9 . The integrated circuit of  claim 1  wherein said dual damascene pattern liner comprise at least two films coupled together.  
     
     
         10 . The integrated circuit of  claim 1  wherein said dual damascene pattern liner comprises a metal film coupled to a dielectric film.  
     
     
         11 . An integrated circuit comprising: 
 a semiconductor substrate;    a front-end structure coupled to said semiconductor substrate;    a single damascene layer coupled to said front-end structure;    a dual damascene layer coupled to said single damascene layer, said dual damascene layer comprising trenches and vias within a dielectric material; and    a dual damascene pattern liner coupled to at least partially between said trenches and said dielectric material but not between said vias and said dielectric material.    
     
     
         12 . The integrated circuit of  claim 11  wherein said dielectric material comprises low-k material.  
     
     
         13 . The integrated circuit of  claim 12  wherein said low-k material comprises OSG.  
     
     
         14 . The integrated circuit of  claim 11  wherein said dual damascene pattern liner comprises a refractory metal.  
     
     
         15 . The integrated circuit of  claim 14  wherein said refractory metal comprises TiN.  
     
     
         16 . The integrated circuit of  claim 11  wherein said dual damascene pattern liner comprises a dielectric film.  
     
     
         17 . The integrated circuit of  claim 16  wherein said dielectric film is SiN.  
     
     
         18 . The integrated circuit of  claim 11  wherein said dual damascene pattern liner comprises at least two films coupled together.  
     
     
         19 . The integrated circuit of  claim 11  wherein said dual damascene pattern liner comprises a metal film coupled to a dielectric film.  
     
     
         20 . A method of manufacturing a semiconductor wafer comprising: 
 forming a front-end structure over a semiconductor substrate;    forming a single damascene back-end structure metal layer over said front-end structure; and    forming a dual damascene back-end structure over said single damascene back-end structure metal layer, said dual damascene back-end structure comprising: 
 forming a via etch stop layer over said single damascene back-end structure metal layer;  
 forming a dielectric layer over said via etch stop layer;  
 forming a cap layer over said dielectric layer;  
 forming a non-photoactive layer over said cap layer;  
 forming a photoresist layer over said non-photoactive layer;  
 patterning said photoresist layer;  
 etching via holes;  
 removing said photoresist layer and said non-photoactive layer;  
 forming a dual damascene pattern liner over said cap layer and within said via holes;  
 forming a non-photoactive layer over said dual damascene pattern liner;  
 forming a photoresist layer over said non-photoactive layer patterning said photoresist layer; and  
 etching trench spaces.  
   
     
     
         21 . The method of  claim 20  wherein said dielectric layer comprises an Inter-Level Dielectric layer and an Inter-Metal Dielectric layer.  
     
     
         22 . The method of  claim 20  wherein said dielectric layer comprises an Inter-Level Dielectric layer, a trench stop layer, and an Inter-Metal Dielectric layer.  
     
     
         23 . The method of  claim 20  wherein said dielectric layer comprises a low-k material.  
     
     
         24 . The method of  claim 20  wherein said step of etching via holes includes etching said via etch stop layer between said via holes and said single damascene back-end structure metal layer.  
     
     
         25 . The method of  claim 20  wherein said step of etching via holes comprises etching partial via holes and then completing an etching of said via holes during said step of etching trench spaces.  
     
     
         26 . The method of  claim 20  further comprising forming at least one additional dual damascene back end structure over said semiconductor substrate.  
     
     
         27 . The method of  claim 20  wherein said step of forming a dual damascene pattern liner comprises forming a multi-layer dual damascene pattern liner.  
     
     
         28 . The method of  claim 27  wherein said multi-layer dual damascene pattern liner comprises at least one metal film and at least one dielectric film.  
     
     
         29 . The method of  claim 20  wherein said dual damascene pattern liner comprises a metal film.  
     
     
         30 . The method of  claim 20  wherein said dual damascene pattern liner comprises a dielectric film.  
     
     
         31 . A method of manufacturing a semiconductor wafer comprising: 
 forming a front-end structure over a semiconductor substrate;    forming a single damascene back-end structure metal layer over said front-end structure; and    forming a dual damascene back-end structure over said single damascene back-end structure metal layer, said dual damascene back-end structure comprising: 
 forming a via etch stop layer over said single damascene back-end structure metal layer;  
 forming a dielectric layer over said via etch stop layer;  
 forming a cap layer over said dielectric layer;  
 forming a non-photoactive layer over said cap layer;  
 forming a photoresist layer over said non-photoactive layer;  
 patterning said photoresist;  
 etching trench spaces;  
 removing said photoresist layer and said non-photoactive layer;  
 forming a dual damascene pattern liner over said cap layer and within said trench spaces;  
 forming a non-photoactive layer over said dual damascene pattern liner;  
 forming a photoresist layer over said non-photoactive layer;  
 patterning said photoresist layer; and  
 etching via holes.  
   
     
     
         32 . The method of  claim 31  wherein said dielectric layer comprises an Inter-Level Dielectric layer and an Inter-Metal Dielectric layer.  
     
     
         33 . The method of  claim 31  wherein said dielectric layer comprises an Inter-Level Dielectric layer, a trench stop layer, and an Inter-Metal Dielectric layer.  
     
     
         34 . The method of  claim 31  wherein said dielectric layer comprises a low-k material.  
     
     
         35 . The method of  claim 31  wherein said step of etching via holes includes etching said via etch stop layer between said via holes and said single damascene back-end structure metal layer.  
     
     
         36 . The method of  claim 31  further comprising forming at least one additional dual damascene back end structure over said semiconductor substrate.  
     
     
         37 . The method of  claim 31  wherein said step of forming a dual damascene pattern liner comprises forming a multi-layer dual damascene pattern liner.  
     
     
         38 . The method of  claim 37  wherein said multi-layer dual damascene pattern liner comprises at least one metal film and at least one dielectric film.  
     
     
         39 . The method of  claim 31  wherein said dual damascene pattern liner comprises a metal film.  
     
     
         40 . The method of  claim 31  wherein said dual damascene pattern liner comprises a dielectric film.