Apparatus and method for providing a clock signal for testing

Abstract

A clock signal driven device has a clock pin for receiving an externally generated clock signal during normal operation. Internal circuitry coupled to the clock pin is responsive to the externally generated clock signal during normal operation. The device also has a clock source, such as a PLL, that provides an internal clock signal, and an internal clock generator that during a test mode of operation generates from the internal clock signal and asserts on the clock pin a test clock signal. The test clock signal has substantially similar signal characteristics to predefined signal characteristics of the externally generated clock signal. The device's internal circuitry is responsive to the test clock signal during the test mode of operation.

What is claimed is:  
     
         1 . A memory controller, comprising: 
 a phase compensation circuit adapted for receiving a first clock signal, the phase compensation circuit configured to use the first clock signal to synchronize data communications between the memory controller and a memory device during a first mode of operation; and    a clock generator circuit coupled to the phase compensation circuit and configured to provide a second clock signal to the phase compensation circuit during a second mode of operation, wherein the first and second clock signals have at least one substantially similar signal characteristic.    
     
     
         2 . The memory controller of  claim 1 , wherein the clock generator circuit provides differential clock signals.  
     
     
         3 . The memory controller of  claim 1 , wherein the first and second clock signals have substantially the same voltage levels.  
     
     
         4 . The memory controller of  claim 1 , wherein the first and second clock signals have substantially the same frequency.  
     
     
         5 . The memory controller of  claim 4 , wherein the frequency is about 400 MHz.  
     
     
         6 . The memory controller of  claim 1 , further comprising: 
 an output driver circuit coupled to the phase compensation circuit and to at least one data output node, the output driver circuit configured to drive outgoing data signals on the data output node.    
     
     
         7 . The memory controller of  claim 6 , further comprising: 
 a drive current control register coupled to the output driver circuit and configured to set an amount of drive current that the output driver circuit uses to drive the outgoing data signal on the data output node.    
     
     
         8 . The memory controller of  claim 6 , further comprising: 
 a slew rate control register coupled to the output driver circuit and storing slew rate control data for configuring the output driver circuit to control slew rates of data signals applied to the data output node.    
     
     
         9 . The memory controller of  claim 1 , further comprising: 
 a clock current register coupled to the clock generator circuit and configured to set an amount of drive current that the clock generator circuit uses to drive the second clock signal on a clock output node.    
     
     
         10 . A memory device, comprising: 
 a phase compensation circuit adapted for receiving a first clock signal, the phase compensation circuit configured to use the first clock signal to synchronize data communications between the memory device and a memory controller during a first mode of operation; and    a clock generator circuit coupled to the phase compensation circuit during a second mode of operation, and configured to provide a second clock signal to the phase compensation circuit, wherein the first and second clock signals have at least one substantially similar signal characteristic.    
     
     
         11 . The memory device of  claim 10 , wherein the clock generator circuit provides differential clock signals.  
     
     
         12 . The memory device of  claim 11 , wherein the clock generator circuit generates two pairs of differential clock signals.  
     
     
         13 . The memory device of  claim 10 , wherein the first and second clock signals have substantially the same voltage levels.  
     
     
         14 . The memory device of  claim 10 , wherein the first and second clock signals have substantially the same frequency.  
     
     
         15 . The memory device of  claim 14 , wherein the frequency is about 400 MHz.  
     
     
         16 . The memory device of  claim 10 , further comprising: 
 an output driver circuit coupled to the phase compensation circuit and to at least one data output node, the output driver circuit configured to drive outgoing data signals on the data output node.    
     
     
         17 . The memory device of  claim 16 , further comprising: 
 a drive current control register coupled to the output driver circuit and configured to set an amount of drive current that the output driver circuit use to drive the outgoing data signal on the data output node.    
     
     
         18 . The memory device of  claim 16 , further comprising: 
 a slew rate control register coupled to the output driver circuit and storing slew rate control data for configuring the output driver circuit to control slew rates of data signals applied to the data output node.    
     
     
         19 . The memory device of  claim 16 , further comprising: 
 a clock current register coupled to the clock generator circuit and configured to set an amount of drive current that the clock generator circuit uses to drive the second clock signal on a clock output node.    
     
     
         20 . A method of providing clock signals for testing a memory controller, comprising: 
 in the memory controller: 
 generating a test clock signal during a first mode of operation, wherein the test clock signal has substantially similar signal characteristics to a clock signal received by the memory controller during a second mode of operation.  
   
     
     
         21 . The method of  claim 20 , wherein the clock signal and the test clock signal are differential clock signals.  
     
     
         22 . The method of  claim 20 , wherein the clock signal and the test clock signal have substantially the same voltage levels.  
     
     
         23 . The method of  claim 20 , wherein the clock signal and the test clock signal have substantially the same frequency.  
     
     
         24 . The method of  claim 23 , wherein the frequency is about 400 MHz.  
     
     
         25 . The method of  claim 20 , further comprising: 
 setting an amount of drive current that a clock generator circuit uses to drive the test clock signal on a clock output node.    
     
     
         26 . A method of providing clock signals for testing a memory device, comprising: 
 in the memory device: 
 generating a test clock signal during a first mode of operation, wherein the test clock signal has substantially similar signal characteristics to a clock signal received by the memory device during a second mode of operation.  
   
     
     
         27 . The method of  claim 26 , wherein the clock signal and the test clock signal have substantially the same voltage levels.  
     
     
         28 . The method of  claim 26 , wherein the clock signal and the test clock signal have substantially the same frequency.  
     
     
         29 . The method of  claim 28 , wherein the frequency is about 400 MHz.  
     
     
         30 . The method of  claim 26 , further comprising: 
 setting an amount of drive current that a clock generator circuit uses to drive the test clock signal on a clock output node.    
     
     
         31 . A memory controller, comprising: 
 means for receiving a clock signal for synchronizing data communications between the memory controller and a memory device during a first mode of operation; and    means for providing a test clock signal during a second mode of operation for testing the memory controller, wherein the clock signal and the test clock signal have at least one substantially similar signal characteristic.    
     
     
         32 . A memory device, comprising: 
 means for receiving a clock signal for synchronizing data communications between the memory device and a memory controller during a first mode of operation; and    means for providing a test clock signal during a second mode of operation for testing the memory device, wherein the clock signal and the test clock signal have at least one substantially similar signal characteristic.