Method of forming organic spacers and using organic spacers to form semiconductor device features

Abstract

A method of forming organic spacers using an N 2 plasma or N 2 containing plasma anisotropic etchant, and using such organic spacers for forming features on a semiconductor structure such as vias having a smaller dimension than can be defined by lithographic techniques Other features formed according to the teachings of this invention include Source/Drain (S/D) areas, LDD/extension areas and graded junctions with larger S/D silicide/contact areas. The process for forming the organic spacers comprises conformally coating a patterned semiconductor structure with an organic material such as, for example, an antireflective coating. The coated structure is then anisotropically etched with N 2 plasma or N 2 containing plasma which forms the organic spacers. Organic spacers may be formed by the method of this invention or any other known method and used to form other device features such as (i) larger S/D contact areas, which may include graded junctions; and (ii) larger S/D contact areas and LDD/extensions, which may also include graded junctions with a single implant step.

1 . A method of forming an organic spacer during a plasma etch comprising the steps of: 
 providing a patterned semiconductor structure;    conformally coating said patterned semiconductor structure with an organic layer; and    anisotropically etching said coated semiconductor structure with N2 plasma to produce said organic spacer.    
     
     
         2 . The method of  claim 1  wherein said step of providing said patterned semiconductor structure comprises the steps of: 
 providing a semiconductor substrate;  
 forming a layer of dielectric material over said semiconductor substrate;  
 covering said layer of dielectric material with a photoresist; and  
 patterning said photoresist.  
 
     
     
         3 . The method of  claim 2  wherein said step of etching further comprises etching through said dielectric layer to said substrate.  
     
     
         4 . The method of  claim 3  wherein said etching through said dielectric substrate forms a contact via and further comprising the step of filing said contact via with a conductive material.  
     
     
         5 . The method of  claim 4  further comprising the step of removing said organic spacer.  
     
     
         6 . The method of  claim 1  wherein said N2 plasma includes an additive selected from the group consisting of Argon and Helium.  
     
     
         7 . The method of  claim 1  wherein said step of providing said patterned semiconductor structure comprises the step of providing a semiconductor substrate having a conductive gate member.  
     
     
         8 . The method of  claim 7  wherein said organic spacers are formed on the sides of said conductive gate and extend from said conductive member to said first and second areas, and further comprising the step of ion implanting said first and second areas to form first and second Source/Drain areas.  
     
     
         9 . The method of  claim 8  wherein a portion of said implantation of ions is through said organic spacer such that an LDD/extension area is formed between the conductive gate and at least one of said Source/Drain areas.  
     
     
         10 . The method of  claim 9  wherein said organic spacer is shaped so that a graded junction is formed between said LDD/extension area and one of said Source/Drain areas.  
     
     
         11 . The method of  claim 8  further comprising the step of removing said organic spacer.  
     
     
         12 . The method of  claim 11  further comprising the step of forming a permanent spacer on the side of said conductive gate suitable for receiving a S/D contact.  
     
     
         13 . The method of  claim 7  wherein said N2 plasma includes an additive selected from the group consisting of Argon and Helium.  
     
     
         14 . The method of  claim 1  wherein said step of coating comprising a step of coating said patterned semiconductor structure with an organic material selected from the group consisting of a photoresist, an antireflective coating (ARC) material.  
     
     
         15 . A method of forming semiconductor features using organic spacers comprising the steps of: 
 providing a semiconductor substrate;    forming a conductive gate member;    forming organic spacers on the sides of said conductive gate member; and    forming Source/Drain areas and a graded junction during a single ion implantation step and without annealing.    
     
     
         16 . The method of  claim 15  wherein a portion of said implantation of ions is through said organic spacer such that an LDD/extension area is formed between the conductive gate and at least one of said Source/Drain areas.  
     
     
         17 . (Cancelled)  
     
     
         18 . The method of  claim 15  wherein an enhanced graded junction is formed with said S/D area in said single implantation step.  
     
     
         19 . The method of  claim 15  further comprising the step of removing said organic spacers.  
     
     
         20 . The method of  claim 19  further comprising the step of forming a permanent spacer on the side of said conductive gate suitable for receiving an S/D contact.  
     
     
         21 . A method of forming semiconductor features using organic spacers comprising the steps of: 
 providing a semiconductor substrate having a conductive gate member;    forming permanent spacers on the sides of said conductive gate member;    forming organic spacers on said permanent spacers; and    forming Source/Drain areas and a graded junction during a single ion implantation step and without annealing.    
     
     
         22 . The method of  claim 24  wherein said single ion implantation step forms an enhanced graded junction with said Source/Drain areas.  
     
     
         23 . The method of  claim 21  wherein LDD/extension areas are formed prior to said step of forming permanent spacers.  
     
     
         24 . The method of  claim 21  wherein a portion of said implantation of ions is through said organic spacer for forming said graded junction.  
     
     
         25 . (Cancelled)  
     
     
         26 . A method of forming semiconductor features using organic spacers comprising the steps of: 
 providing a semiconductor substrate;    forming a conductive gate member;    forming organic spacers on the sides of said conductive gate member; and    forming a Source/Drain area and an LDD/extension area at the same time during a single ion implantation step and without annealing.    
     
     
         27 . The method of  claim 26  wherein a portion of said implantation of ions is through said organic spacer so as to form an enhanced graded junction between said LDD/extension area and said Source/Drain areas.  
     
     
         28 . The method of  claim 26  further comprising the step of removing said organic spacers.  
     
     
         29 . The method of  claim 28  further comprising the step of forming a permanent spacer on the side of said conductive gate suitable for receiving an S/D contact.  
     
     
         30 . The method of  claim 15  wherein LDD/extension areas are formed prior to said step of forming organic spacers.  
     
     
         31 . The method of  claim 21  further comprising the step of removing said organic spacers.  
     
     
         32 . A method of forming semiconductor features using organic spacers comprising the steps of: 
 providing a semiconductor substrate;    forming a conductive gate member;    forming organic spacers on the sides of said conductive gate member; and    forming Source/Drain areas and a graded junction at the same time during a single ion implantation step.    
     
     
         33 . A method of forming semiconductor features using organic spacers comprising the steps of: 
 providing a semiconductor substrate having a conductive gate member;    forming permanent spacers on the sides of said conductive gate member;    forming organic spacers on said permanent spacers; and    forming Source/Drain areas and a graded junction at the same time during a single ion implantation step.