Direct conversion delta-sigma receiver

Abstract

A wireless receiver receives a wireless signal by inverting the polarity of an incoming waveform on every one half clock cycle of a conversion clock to produce a commutated waveform and converting said commutated waveform to a series of representative digital values using a delta-sigma modulator clocked by said conversion clock. In this way, the receiver operates over a large dynamic range and the use of automatic gain control in the front end may be eliminated.

1 - 19  (Canceled)  
     
     
         20 . A circuit comprising: 
 a voltage follower configured to receive an incoming waveform;    a transistor network having a first input coupled to an output of said linearizing operational amplifier and having a second input coupled to said incoming waveform, said linearizing operational amplifier and said first complementary transistor network configured to produce a pair of complementary currents that are linearly related to an input voltage level of said incoming waveform;    a first current source coupled to said transistor network and configured to provide a fixed current through said first transistor network;    a commutator network coupled to a clock signal and coupled to said pair of complementary currents that are linearly related to said input voltage level of said incoming waveform;    a second current source configured to produce a fixed current; and    a switching network coupled to said second current source, having complementary input ports configured to be coupled to logic values and configured to produce complementary switched currents, wherein said complementary switched currents are coupled to said commutator network in order to control together complementary voltage outputs produced by the circuit.    
     
     
         21 . The circuit of  claim 20  wherein: 
 said voltage follower comprises a linearizing operational amplifier in a non-inverting unity follower configuration.  
 
     
     
         22 . A method of receiving a wireless signal comprising a baseband signal modulated on a carrier frequency signal, the method comprising: 
 alternatingly multiplying a radio frequency waveform by a positive factor and a negative factor in accordance with a first clock to produce a commutated waveform including a low frequency component;    converting the low frequency component to a digital form.    
     
     
         23 . The method of  claim 22  wherein said first clock has a frequency approximately equal to said carrier frequency.  
     
     
         24 . The method of  claim 22  wherein said converting step comprises producing a digital signal at a sample rate that is approximately equal to said carrier frequency.  
     
     
         25 . The method of  claim 22  wherein said converting step is triggered by an edge of a conversion clock, said conversion clock and said first clock being at the same frequency.  
     
     
         26 . The method of  claim 25  wherein said converting step is performed using a delta-sigma converter.  
     
     
         27 . The method of  claim 26  wherein said positive factor is +1 and said negative factor is −1.  
     
     
         28 . A wireless receiver for receiving an incoming radio frequency signal comprising: 
 a commutator; and    a single-bit modulator coupled to an output of said commutator;    wherein said commutator and said single-bit modulator are both clocked at a common conversion frequency.    
     
     
         29 . The wireless receiver of  claim 28  wherein said common conversion frequency is approximately equal to a carrier frequency of said radio frequency signal, whereby a signal modulated on said carrier frequency is converted directly down to a baseband signal range without the need to first convert the radio frequency signal to an intermediate frequency.  
     
     
         30 . The wireless receiver of  claim 28  wherein said modulator comprises a delta-sigma modulator having an order of greater than one.  
     
     
         31 . The wireless receiver of  claim 28  wherein said receiver is a receiver in a personal communication system, and said incoming radio frequency signal has a carrier frequency of approximately 2 GHz.  
     
     
         32 . The wireless receiver of  claim 31  wherein said receiver has no automatic gain control circuitry and is implemented on a single integrated circuit substrate.  
     
     
         33 . The wireless receiver of  claim 31  further comprising: 
 a wideband, low pass decimation filter for filtering an output of said modulator.