Circuit board
Abstract
This invention relates to circuit boards and methods of fabricating circuit boards. A circuit board includes a core layer and a surface layer. The core layer includes a number of fibers and the surface layer has a thickness that is between about 10% and about 30% of the circuit board thickness. Including fibers in the core layer increases the strength of the circuit board. The surface layer is essentially free of fibers and relatively thick. The thickness of the surface layer inhibits the formation of cracks in the circuit board, which improves the reliability of circuits and systems coupled to the circuit board.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A system comprising:
a processor; a die having a number of memory circuits, at least one of the number of memory circuits being coupled to the processor; and a circuit board coupled to the die, the circuit board having a surface and a thickness, and the circuit board including a number of embedded fibers such that the number of embedded fibers are located at a distance of between about 10% to 30% from the surface of the circuit board.
2 . The system of claim 1 , wherein the processor comprises a microprocessor.
3 . The system of claim 1 , wherein the processor comprises a digital signal processor.
4 The system of claim 1 , wherein the number of memory circuits comprises a static random access memory (SRAM).
5 . The system of claim 1 , wherein the number of memory circuits comprises a dynamic random access memory (DRAM).
6 . A system comprising:
a processor; a die having a number of memory circuits, at least one of the number of memory circuits being coupled to the processor; and a circuit board coupled to the die, the circuit board having a first surface, a second surface, and a thickness, and the circuit board including a number of embedded fibers such that the number of embedded fibers are located at a distance of between about 10% and about 15% from the first surface and at a distance of between about 10% and about 15% from the second surface.
7 . The system of claim 6 , wherein the processor is a reduced instruction set computer (RISC).
8 . The system of claim 6 , wherein the number of embedded fibers is one.
9 . The system of claim 6 , wherein the number of memory circuits include electrically eraseable programmable (EEPROM) memory circuits.
10 . A system comprising:
a processor; a die having a number of memory circuits, at least one of the number of memory circuits being coupled to the processor; and a circuit board coupled to the die, the circuit board having a first surface, a second surface, and a thickness, and the circuit board including a number of embedded fibers, each of the number of embedded fibers having a thickness of between about 0.010 inches and 0.020 inches, the number of embedded fibers are located at a distance of between about 10% to 15% from the first surface and at a distance of between about 10% to 15% from the second surface.
11 . The system of claim 10 , wherein the processor is a digital signal processor (DSP).
12 . The system of claim 10 , wherein the circuit board is thermally coupled to the die.
13 . The system of claim 10 , wherein the circuit board includes polymeric compounds.
14 . A method of fabricating a circuit board having a circuit board thickness, the method comprising:
forming a core layer including a number of fibers; and forming a surface layer on the core layer, the surface layer having a surface layer thickness that is between about 10% and about 30% of the circuit board thickness, the surface layer being free of fibers.
15 . The method of claim 14 , wherein forming a core layer including a number of fibers comprises:
embedding the number of fibers in a resin.
16 . The method of claim 14 , wherein forming a core layer including a number of fibers comprises:
embedding the number of fibers in a polymeric composite material.
17 . The method of claim 14 , forming a core layer including a number of fibers comprises:
embedding the number of fibers in phenolic.
18 . A method of fabricating a circuit board having a circuit board thickness, the method comprising:
forming a core layer including a number of fibers; and forming a surface resin layer on the core layer, the surface layer having a surface layer thickness that is between about 10% to 30% of the circuit board thickness.
19 . The method of claim 18 , further comprising:
forming a number of slots in the circuit board.
20 . The method of claim 18 , further comprising:
mounting a die using an adhesive over each of the number of slots.
21 . A method of fabricating a circuit board having a circuit board thickness comprising:
forming a core layer including a number of fibers; forming a first layer on the core layer, the first layer having a thickness between about 10% and about 15% of the circuit board thickness and the first layer being free of fibers; and forming a second layer on the core layer, the second having a thickness that is between about 10% and about 15% of the circuit board thickness.
22 . A method of fabricating a circuit board having a circuit board thickness comprising:
forming a core layer including a number of fibers; forming a first layer on a first side of the core layer, the first layer having a thickness between about 10% and about 15% of the circuit board thickness and the first layer being free of fibers; and forming a second layer on a second side of the core layer, the second having a thickness that is between about 10% and about 15% of the circuit board thickness.
23 . A method of fabricating a circuit board having a circuit board thickness comprising:
forming a core layer including a number of fibers; forming a first resin layer on the core layer, the first resin layer having a thickness between about 10% and about 15% of the circuit board thickness; and forming a second resin layer on the core layer, the second resin layer having a thickness that is between about 10% and about 15% of the circuit board thickness.
24 . The method of claim 23 , wherein forming the core layer includes embedding the fibers in a resin layer.Join the waitlist — get patent alerts
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