Apparatus and method for molding a semiconductor die package with enhanced thermal conductivity

Abstract

A method and apparatus for assembling and packaging semiconductor die assemblies utilizes a coating element such as a wafer back side laminate formed on a back side of a semiconductor die is disclosed. The coating element may be formed from a somewhat compressible and, optionally, resilient material, which seals against a surface of a mold cavity while the semiconductor die assembly is being encapsulated. In this manner, the coating element prevents encapsulant material from covering at least a portion of the back side of the semiconductor die to prevent encapsulant flashing over the back side and thus improve heat dissipation characteristics of the packaged semiconductor die during operation.

1 . A semiconductor device assembly, comprising: 
 at least one semiconductor die;    a carrier positioned adjacent to an active surface of the at least one semiconductor die and including at least a portion oriented substantially parallel thereto;    at least one intermediate conductive element electrically connecting at least one bond pad of the at least one semiconductor die and a corresponding contact of the carrier;    an encapsulant covering at least an outer periphery of the at least one semiconductor die; and    a compressible coating element on at least a portion of a back side of the at least one semiconductor die, at least a substantial portion of the compressible coating element being exposed.    
     
     
         2 . The semiconductor device assembly of  claim 1 , wherein the compressible coating element is sized and shaped in substantial conformance to a size and shape of the back side of the at least one semiconductor die.  
     
     
         3 . The semiconductor device assembly of  claim 1 , wherein the compressible coating element has an outer surface substantially coplanar with an outer surface of the encapsulant.  
     
     
         4 . The semiconductor device assembly of  claim 1 , wherein an outer surface of the compressible coating element projects slightly beyond a surrounding outer surface of the encapsulant.  
     
     
         5 . The semiconductor device assembly of  claim 1 , wherein the compressible coating element substantially covers the back side of the at least one semiconductor die.  
     
     
         6 . The semiconductor device assembly of  claim 1 , wherein the compressible coating element includes an outer boundary lying substantially along a periphery of the back side of the at least one semiconductor die.  
     
     
         7 . The semiconductor device assembly of  claim 6 , wherein the compressible coating element is configured as a frame.  
     
     
         8 . The semiconductor device assembly of  claim 6 , wherein the compressible coating element is configured so that a nonperipheral portion of the back side of the at least one semiconductor die is exposed.  
     
     
         9 . The semiconductor device assembly of  claim 6 , wherein the compressible coating element is configured so that a central portion of the back side is exposed.  
     
     
         10 . The semiconductor device assembly of  claim 1 , wherein the compressible coating element comprises a compliant or resilient material.  
     
     
         11 . The semiconductor device assembly of  claim 1 , wherein the compressible coating element comprises a preformed film.  
     
     
         12 . The semiconductor device assembly of  claim 11 , wherein the preformed film is adhered to the at least a portion of the back side with an adhesive.  
     
     
         13 . The semiconductor device assembly of  claim 1 , wherein the compressible coating element is formed on the at least a portion of the back side in a nonsolid state and subsequently at least substantially solidified.  
     
     
         14 . The semiconductor device assembly of  claim 1 , wherein the compressible coating element is formulated to exhibit a coefficient of thermal expansion similar to a coefficient of thermal expansion of the at least one semiconductor die.  
     
     
         15 . The semiconductor device assembly of  claim 14 , wherein the compressible coating element comprises a preformed film filled with silicon particles.  
     
     
         16 . The semiconductor device assembly of  claim 14 , wherein the compressible coating element is formed on the at least a portion of the back side in a nonsolid mass filled with silicon particles and subsequently at least substantially solidified.  
     
     
         17 . The semiconductor device assembly of  claim 1 , wherein the encapsulant substantially encapsulates the at least one intermediate conductive element.  
     
     
         18 . The semiconductor device assembly of  claim 1 , wherein the encapsulant covers at least a portion of the carrier.  
     
     
         19 . The semiconductor device assembly of  claim 1 , wherein the carrier includes at least one aperture through which the at least one bond pad of the at least one semiconductor die is exposed and the at least one intermediate conductive element extends through the at least one aperture between the at least one bond bad and the corresponding contact of the carrier.  
     
     
         20 . The semiconductor device assembly of  claim 1 , wherein the corresponding contact of the carrier is on a surface of the carrier facing the active surface of the at least one semiconductor die and in alignment therewith and the carrier is spaced from the at least one semiconductor die by the at least one intermediate conductive element.  
     
     
         21 . The semiconductor device assembly of  claim 20 , wherein the at least one bond pad comprises an array of bond pads.  
     
     
         22 . The semiconductor device assembly of  claim 21 , wherein the at least one intermediate conductive element comprises a conductive bump, a conductive pillar, or a conductive pin.  
     
     
         23 . The semiconductor device assembly of  claim 20 , wherein the encapsulant extends between the carrier and the at least one semiconductor die and encapsulates the at least one intermediate conductive element therebetween.  
     
     
         24 . The semiconductor device assembly of  claim 1 , wherein the carrier comprises a lead frame and the corresponding contact comprises a lead finger.  
     
     
         25 . A mold assembly configured for use in packaging a semiconductor die on a carrier, the mold assembly comprising: 
 at least first and second mold sections to be assembled with one another;    at least one cavity segment formed in each of the first and second mold sections, the at least one cavity segment in each of the first and second mold sections being sized and configured, when in alignment, to define at least one cavity configured to receive a semiconductor die on a carrier;    a portion of an inner surface of the at least one cavity segment of at least one of the first and second mold sections comprising a surface finish of enhanced smoothness relative to at least one other portion of the inner surface.    
     
     
         26 . The mold assembly of  claim 25 , wherein the portion of the inner surface is substantially centrally located in the at least one cavity segment.  
     
     
         27 . The mold assembly of  claim 25 , wherein the portion of the inner surface is positioned on the inner surface to correspond with a location of a back side of the semiconductor die on the carrier when received in the at least one cavity segment.  
     
     
         28 . The mold assembly of  claim 27 , wherein the portion of the inner surface has an outer periphery substantially coincident with the back side of the semiconductor die.  
     
     
         29 . The mold assembly of  claim 25 , wherein the surface finish of enhanced smoothness of the portion of the inner surface comprises a ground finish, a lapped finish or a polished finish.  
     
     
         30 . The mold assembly of  claim 25 , wherein the surface finish of enhanced smoothness of the portion of the inner surface is shaped as a frame.  
     
     
         31 . An intermediate structure for a semiconductor device assembly, comprising: 
 a semiconductor die secured to a carrier and operably coupled thereto for external electrical communication therethrough; and    a compressible coating element positioned on a back side of the semiconductor die adjacent to at least a peripheral edge of the back side, the compressible coating element comprising a material for sealing between the back side of the semiconductor die and an inner surface of a mold cavity to prevent an encapsulant material introduced into the mold cavity from covering the back side of the semiconductor die during encapsulation of the intermediate structure in the mold cavity.    
     
     
         32 . The intermediate structure of  claim 31 , wherein the compressible coating element is sized and configured to substantially cover the back side of the semiconductor die.  
     
     
         33 . The intermediate structure of  claim 31 , wherein the compressible coating element is sized and configured to substantially overlie the back side of the semiconductor die proximate a peripheral edge thereof.  
     
     
         34 . The intermediate structure of  claim 33 , wherein the compressible coating element is sized and configured so that a portion of the back side of the semiconductor die is exposed.  
     
     
         35 . The intermediate structure of  claim 31 , wherein the compressible coating element comprises a compliant or a resilient material.  
     
     
         36 . The intermediate structure of  claim 31 , wherein the compressible coating element exhibits a coefficient of thermal expansion similar to a coefficient of thermal expansion of the semiconductor die.  
     
     
         37 . An electronic system comprising: 
 a processor in communication with at least one input device and at least one output device; and    a semiconductor assembly, comprising: 
 at least one semiconductor die;  
 a carrier positioned adjacent to an active surface of the at least one semiconductor die and oriented substantially parallel thereto, the carrier being in communication with at least one of the processor, the at least one input device, and the at least one output device;  
 at least one intermediate conductive element electrically connecting a bond pad of the at least one semiconductor die and a corresponding contact of the carrier;  
 an encapsulant covering at least an outer periphery of the at least one semiconductor die; and  
 a compressible coating element on a back side of the at least one semiconductor die, at least a substantial portion of the compressible coating element being exposed.  
   
     
     
         38 . The electronic system of  claim 37 , wherein the compressible coating element comprises a layer that substantially covers the back side of the at least one semiconductor die.  
     
     
         39 . The electronic system of  claim 37 , wherein the compressible coating element comprises a layer that overlies the back side at least proximate an outer periphery of the back side of the at least one semiconductor die.  
     
     
         40 . The electronic system of  claim 39 , wherein the layer is configured so that a portion of the back side of the at least one semiconductor die is exposed.  
     
     
         41 . The electronic system of  claim 37 , wherein the compressible coating element is positioned on the back side of the at least one semiconductor die adjacent to an outer periphery thereof, a central portion of the back side remaining exposed.  
     
     
         42 . The electronic system of  claim 37 , wherein the compressible coating element comprises a compliant or resilient material.  
     
     
         43 . The electronic system of  claim 37 , wherein the compressible coating element exhibits a coefficient of thermal expansion similar to a coefficient of thermal expansion of the at least one semiconductor die.  
     
     
         44 . The electronic system of  claim 37 , wherein the encapsulant substantially encapsulates the at least one intermediate conductive element.