Processor, compiling apparatus, and compile program recorded on a recording medium

Abstract

Each of registers R 0 to R 31 is divided into the upper 32-bit area and the lower 32-bit area. A register writing control unit 431 outputs information to the selectors 4321 and 4322 on the registers and the locations (upper and lower areas) in which data is written by the instructions that have issued in one cycle. Each of the selectors 4321 and 4322 selects one out of pieces of data that have been output from first, second, and third arithmetic operation units 44, 45 , and 46 and writes the selected data in the upper or lower area in one register. A dependency analysis unit 110 in a compiling apparatus considers the upper and lower registers in one 64-bit register as separate resources, analyzes the data dependency relations between the instructions, and generates a dependency graph that indicates the data dependency relations. A instruction rearrangement unit 111 rearranges the instructions and generates execution codes using the dependency graph.

1 - 20 . (canceled)  
     
     
         21 . A processor comprising: 
 a destination register including a first area and a second area; and    a plurality of operation units able to execute a first operation and a second operation in parallel,    wherein the first operation includes storing data in the first area of the destination register, and    wherein the second operation has a different function from the first operation and includes storing data in the second area of the destination register.    
     
     
         22 . The processor of  claim 21 , wherein the plurality of operation units comprise: 
 a first operating unit able to execute the first operation; and    a second operating unit able to execute the second operation,    wherein the second operating unit id different from the first operating unit.    
     
     
         23 . The processor of  claim 21 , further comprising: 
 a first source register storing first data; and    a second source register storing second data,    wherein the first operation includes referring the first data and the second operation includes referring the second data.    
     
     
         24 . The processor of  claim 22 , 
 wherein the first source register and the destination register have the same bit length,    wherein a bit place of the first area in the destination register is higher [upper] than a bit place where the first data is stored in the first source register.    
     
     
         25 . The processor of  claim 21 , further comprising: 
 a decoder decoding an instruction and outputting a decoded information,    wherein the information indicate the destination register and an are of the destination register.    
     
     
         26 . The processor of  claim 25 , wherein the processor is a VLIW processor.  
     
     
         27 . A processing method comprising: 
 executing a first operation in order to create a first data;    executing a second operation, which has a different function than the first operation, in order to create a second data; and    storing the first data and the second data to the same destination register in parallel.    
     
     
         28 . The processing method of  claim 26 , 
 wherein the first data is stored in a first area of the destination register and second data is stored in a second area of the destination register,    wherein the first area and the second area are not overlapped.    
     
     
         29 . The processing method of  claim 27 , further comprising: 
 retrieving a first source data for the first operation from the first source register; and    retrieving a second source data for the second operation, the second source data is not stored in the first source register.    
     
     
         30 . The processing method of  claim 28 , 
 wherein the first source register and the destination register have the same bit length, and a function of the first operation is changing a bit place from the first source data to the first data.