Clock divider and clock dividing method for a DLL circuit

Abstract

A clock divider for a DLL circuit can reduce the power consumption by reducing the number of times of phase comparison in the DLL circuit when a synchronous memory device is in a power-down mode. The clock divider includes M dividers connected in series, and a power-down controller for receiving an output signal of the (M−1)-th divider and an output signal of the M-th divider and selectively outputting the output signals. The respective dividers divide a frequency of a clock signal inputted to the respective dividers into ½, and the output signal of the power-down controller has a frequency obtained by dividing the frequency of the clock signal inputted to the first divider into ½ M or ½ (M−1) in accordance with a logic level of a control signal. The output signal of the third divider is selected in the same manner as the conventional clock divider in the case that the memory device is in a non-power-down mode, but the output signal of the fourth divider is selected in the case that the memory device is in the power-down mode in which the power consumption of the memory device is reduced, thereby reducing the current loss of the DLL circuit.

1 . A clock divider for a dll (delay lock loop) circuit of a synchronous memory device for synchronization of an external input clock with an internal input clock, the clock divider comprising: 
 M (where M is an integer that is larger than 2) dividers connected in series; and    a power-down controller for receiving an output signal of the (M−1)-th divider and an output signal of the M-th divider, and selectively outputting the output signals;    wherein the respective dividers divide a frequency of a clock signal inputted to the respective dividers into {fraction (1/2)}.    
     
     
         2 . The clock divider as claimed in  claim 1 , wherein the output signal of the power-down controller has a frequency obtained by dividing the frequency of the clock signal inputted to the first divider into ½ M  or ½ (M−1)  in accordance with a logic level of a control signal.  
     
     
         3 . The clock divider as claimed in  claim 2 , wherein if the logic level of the control signal is a first state (high level), the output signal of the power-down controller becomes the output of the (M−1)-th divider, and if the logic level of the control signal is a second state (low level), the output signal of the power-down controller becomes the output of the M-th divider.  
     
     
         4 . The clock divider as claimed in  claim 3 , wherein the control signal is a clock enable signal used in the synchronous memory device.  
     
     
         5 . The clock divider as claimed in  claim 1 , wherein a pulse width of a high-level state of the output signal of the first divider is the same as a period of the input signal of the first divider, and a pulse width of a low-level state of output signals of the second to M-th dividers is the same as the period of the input signal of the first divider.  
     
     
         6 . The clock divider as claimed in  claim 4 , wherein the power-down controller comprises two transmission gates, and the two transmission gates are selectively turned on/off according to the control signal.  
     
     
         7 . A clock dividing method for a DLL (Delay Lock Loop) circuit of a synchronous memory device for synchronization of an external input clock with an internal input clock, the method comprising the steps of: 
 selectively outputting an output signal of a (M−1)th divider and an output signal of an M-th divider among M dividers, connected in series, for respectively dividing a frequency of the input clock signal into {fraction (1/2)}.    
     
     
         8 . The clock divider as claimed in  claim 2  wherein a pulse width of a high-level state of the output signal of the first divider is the same as a period of the input signal of the fiLst divider, and a pulse width of a low-level state of output signals of the second to M-th dividers is the same as the period of the input signal of the first divider.  
     
     
         9 . The clock divider as claimed in  claim 8 , wherein the power-down controller comprises two transmission gates, and the two transmission gates are selectively turned on/off according to the control signal.  
     
     
         10 . The clock divider as claimed in  claim 3  wherein a pulse width of a high-level state of the output signal of the first divider is the same as a period of the input signal of the first divider, and a pulse width of a low-level state of output signals of the second to M-th dividers is the same as the period of the input signal of the first divider.  
     
     
         11 . The clock divider as claimed in  claim 10 , wherein the power-down controller comprises two transmission gates, and the two transmission gates are selectively turned on/off according to the control signal.  
     
     
         12 . The clock divider as claimed in  claim 4  wherein a pulse width of a high-level state of the output signal of the first divider is the same as a period of the input signal of the first divider, and a pulse width of a low-level state of output signals of the second to M-th dividers is the same as the period of the input signal of the first divider.