Metal oxide semiconductor field effect transistors (MOSFETs) including recessed channel regions and methods of fabricating the same

Abstract

Unit cells of metal oxide semiconductor (MOS) transistors are provided having an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor includes a source region, a drain region and a gate. The gate is between the source region and the drain region. A channel region is provided between the source and drain regions. The channel region has a recessed region that is lower than bottom surfaces of the source and drain regions. Related methods of fabricating transistors are also provided.

That which is claimed is:  
     
         1 . A unit cell of a metal oxide semiconductor (MOS) transistor, comprising: 
 an integrated circuit substrate;    a MOS transistor on the integrated circuit substrate, the MOS transistor having a source region, a drain region and a gate, the gate being between the source region and the drain region; and    a channel region between the source and drain regions, the channel region having a recessed region that is lower than bottom surfaces of the source and drain regions.    
     
     
         2 . The unit cell of  claim 1 , further comprising first and second insulation patterns on the integrated circuit substrate, wherein the first and second insulation patterns are provided between the source region and drain region, respectively, and the integrated circuit substrate and wherein the first and second insulation patterns contact at least a portion of the bottom surface of the source region and the bottom surface of the drain region, respectively.  
     
     
         3 . The unit cell of  claim 2 , wherein the gate further comprises: 
 a gate insulation layer on the channel region; and    a gate pattern on the gate insulation layer, the gate pattern having sidewalls adjacent to the source and drain regions, and wherein the first and second insulation patterns have sidewalls that are self-aligned to the sidewalls of the gate pattern.    
     
     
         4 . The unit cell of  claim 3 , wherein the gate pattern is provided in a gate opening on the integrated circuit substrate and wherein the gate pattern comprises: 
 first and second inner spacers on sidewalls of the gate opening; and    a conductive pattern on the first and second inner spacers and the gate insulation layer.    
     
     
         5 . The unit cell of  claim 1  further comprising an isolation layer on the integrated circuit substrate that defines an active region of the integrated circuit substrate.  
     
     
         6 . The unit cell of  claim 5 , wherein the insulation pattern is electrically coupled to the isolation layer.  
     
     
         7 . The unit cell of  claim 6 , wherein a bottom surface of the isolation layer is lower than a bottom surface of the insulation pattern.  
     
     
         8 . A method of forming a unit cell of a metal oxide semiconductor (MOS) transistor comprising: 
 forming a MOS transistor on an integrated circuit substrate, the MOS transistor having a source region, a drain region and a gate, the gate being between the source region and the drain region; and    forming a channel region between the source and drain regions, the channel region having a recessed region that is lower than bottom surfaces of the source and drain regions.    
     
     
         9 . The method of  claim 8 , further comprising forming first and second insulation patterns on the integrated circuit substrate between the source region and drain region, respectively, and the integrated circuit substrate such that the first and second insulation patterns contact at least a portion of the bottom surface of the source region and the bottom surface of the drain region, respectively.  
     
     
         10 . The method of  claim 9 , wherein forming the gate further comprises: 
 forming a gate insulation layer on the channel region; and    forming a gate pattern on the gate insulation layer, the gate pattern having sidewalls adjacent to the source and drain regions, and wherein the first and second insulation patterns have sidewalls that are self-aligned to the sidewalls of the gate pattern.    
     
     
         11 . The method of  claim 10 , wherein the gate pattern is formed in a gate opening on the integrated circuit substrate and wherein forming the gate pattern further comprises: 
 forming first and second inner spacers on sidewalls of the gate opening; and    forming a conductive pattern on the first and second inner spacers and the gate insulation layer.    
     
     
         12 . The method of  claim 8  further comprising forming an isolation layer on the integrated circuit substrate that defines an active region of the integrated circuit substrate.  
     
     
         13 . The unit cell of  claim 12 , wherein a bottom surface of the isolation layer is lower than a bottom surface of the insulation pattern  
     
     
         14 . A transistor comprising: 
 an integrated circuit substrate having an active region defined thereon;    spaced apart source and drain regions on the active region of the integrated circuit substrate;    a channel region between the source and drain regions, the channel region having a low recessed region relative to depths of the source and drain regions;    a gate insulation layer formed on the channel region;    a gate pattern formed on the gate insulation layer, the gate pattern having sidewalls adjacent to the source and drain regions; and    an insulation pattern contacting bottom surfaces of the source and drain regions, the insulation region having sidewalls self-aligned to the sidewalls the gate pattern.    
     
     
         15 . A method of fabricating a transistor comprising: 
 forming a first epitaxial layer on an integrated circuit substrate;    forming a second epitaxial layer on the first epitaxial layer; and    forming a mask layer on the second epitaxial layer;    forming a gate opening in the first epitaxial layer, the second epitaxial layer and the mask layer by patterning the first and second epitaxial layers and the mask layer;    forming a third epitaxial having a low recess region relative to a bottom surface of the second epitaxial layer on the integrated circuit substrate;    forming a gate insulation layer on the third epitaxial layer;    forming a gate pattern in the gate opening;    removing the first epitaxial layer to expose the bottom surface of the second epitaxial layer and a portion of the third epitaxial layer; and    forming an insulation layer in a gap region between the second epitaxial layer and the integrated circuit substrate.    
     
     
         16 . The method of  claim 15 , further comprising implanting impurities in the third epitaxial layer using the mask layer as an ion implantation mask.  
     
     
         17 . The method of  claim 15  further comprising: 
 removing the mask layer; and  
 forming source and drain regions on the second epitaxial layer by implanting impurities using the gate pattern as the ion implantation mask.  
 
     
     
         18 . The method of  claim 15  further comprising forming first and second inner spacers on sidewalls of the gate opening before forming the gate pattern.  
     
     
         19 . A method of fabricating a transistor comprising: 
 forming a sacrificial pattern having an opening defining an active region on an integrated circuit substrate;    forming a first epitaxial layer and a second epitaxial layer on a portion of the integrated circuit substrate exposed by the opening;    forming a mask layer on the integrated circuit substrate;    forming a gate opening by patterning the first and second epitaxial layers;    forming a third epitaxial layer on the portion of the integrated circuit substrate exposed by the opening, the third epitaxial layer having a low recess region relative to a bottom surface of the second epitaxial layer;    forming a gate insulation layer oil the third epitaxial layer;    forming a gate pattern in the gate opening;    removing the mask layer and the sacrificial pattern;    removing the first epitaxial layer to expose the bottom surface of the second epitaxial layer and a portion of the third epitaxial layer; and    forming an oxide layer in a gap region between the second epitaxial layer and the integrated circuit substrate.    
     
     
         20 . The method of  claim 19  further comprising: 
 forming a channel region by implanting impurities using the mask layer as an ion implantation mask; and  
 forming source and drain regions in the second epitaxial layer by implanting impurities in the second epitaxial layer using the gate pattern as the ion implantation mask.  
 
     
     
         21 . A method of fabricating a transistor comprising: 
 forming a first epitaxial layer on an integrated circuit substrate;    forming a second epitaxial layer on the first epitaxial layer;    forming a mask layer on the second epitaxial layer;    forming a trench by patterning the first epitaxial layer, the second epitaxial layer, the mask layer and the integrated circuit substrate to define an active region;    forming an isolation layer in the trench;    forming a gate opening by patterning the first epitaxial layer, the second epitaxial layer and a mask layer of the active region to expose at least a portion of the integrated circuit substrate;    forming a third epitaxial layer on the exposed portion of the integrated circuit substrate;    forming a gate insulation layer on the third epitaxial layer;    forming a gate pattern in the gate opening;    removing a portion of the isolation layer to expose a portion of the first epitaxial layer;    removing the first epitaxial layer to expose a bottom surface of the second epitaxial layer and a portion of the third epitaxial layer;    forming an insulation layer on a surface of the integrated circuit substrate and in a gap region between the second epitaxial layer and the active region; and    removing the mask layer to expose the second epitaxial layer on both sides of the gate pattern.    
     
     
         22 . The method of  claim 21  further comprising: 
 forming a channel region in the integrated circuit substrate exposed by the gate opening by implanting impurities using the mask layer as an ion implantation mask; and  
 forming source and drain regions in the exposed portions of the second epitaxial layer by implanting impurities using the gate pattern as the ion implantation mask.  
 
     
     
         23 . A method of fabricating a transistor comprising: 
 forming a first epitaxial layer on an integrated circuit substrate;    forming a second epitaxial layer on the first epitaxial layer;    forming a mask layer on the second epitaxial layer;    patterning the first epitaxial layer, the second epitaxial layer and the mask layer to form a gate opening exposing at least a portion of the integrated circuit substrate;    forming a third epitaxial layer on the exposed portion of the integrated circuit substrate;    forming a gate insulation layer on the third epitaxial layer;    forming a conductive layer in the gate opening on the mask layer;    patterning the first and second epitaxial layers, the mask layer and the conductive layer to define an active region; removing the first epitaxial layer to expose a portion of the third epitaxial layer and a bottom of the second epitaxial layer to define an active region;    forming an insulation layer on the integrated circuit substrate and in a gap region between the second epitaxial layer and the active region;    exposing the mask layer by sequentially polishing the insulation layer and the conductive layer and simultaneously forming a gate pattern in the gate opening and forming an isolation layer surrounding bottom of the gate pattern and the mask layer; and    removing the mask layer to expose the second epitaxial layer on both sides of the gate pattern.    
     
     
         24 . The method of  claim 23  further comprising: 
 forming a channel region on the exposed portion of the integrated circuit substrate by implanting impurities using the mask layer as an ion implantation mask; and  
 forming source and drain regions in the exposed portion of the second epitaxial layer by implanting impurities in the exposed portion of the second epitaxial layer using the gate pattern as the ion implantation.  
 
     
     
         25 . The method of  claim 23 , wherein patterning the first epitaxial layer is followed by forming a trench further defining the active region by continuously patterning a part of the integrated circuit substrate.  
     
     
         26 . The method of  claim 23 , further comprising forming a gate line contacting the gate pattern and on the isolation layer.