Signal processing system for reducing power consumption

Abstract

A low power audio processor is disclosed which includes a bit stream processing unit for performing bit processing for an applied audio stream and for decoding the bit processed audio stream to have a format conducive to digital signal processing; a digital signal processing unit for receiving the decoded data from the bit stream processing unit to perform digital signal processing; a post processing unit for post processing audio data from the digital signal processing unit to output final audio data; and a host interface unit for interfacing with an external device to provide an audio parallel stream from the external device to the bit stream processing unit. The audio signal processor also includes a power control unit for determining the idle state for each of the bit stream processing unit, the digital signal processing unit and the post processing unit in response to: (a) a request signal and an acknowledge signal between the digital signal processing unit and the post processing unit, (b) a power down signal, and (c) a source clock to output the determined power state as a power mode signal; and an internal clock signal generator for generating clock signals, in response to the power mode signal and for outputting the clock signals to respective one of the bit stream processor, the digital signal processor and the post processor.

1 - 4 . (cancelled)  
     
     
         5 . Apparatus for generating a plurality of control clocks in response to a power state of a plurality of processing units, comprising: 
 a first multiplexor for selectively outputting one of a DC level and a source clock in response to a power down signal;    a branch for branching the output of the first multiplexor into a predetermined number of branches; and    a plurality of multiplexors, each for selecting respective ones of the clock signals from the branch and the DC level in response to the power state of a corresponding one of the plurality of processing units and outputting the selected signal to the corresponding processing unit.    
     
     
         6 . The Apparatus as recited in  claim 5 , further comprising a logic device for AND operating the outputs of the plurality of multiplexors to drive a memory device.  
     
     
         7 . A signal processing system for reducing power consumption, comprising: 
 a plurality of processing units;    an internal clock signal generator unit for receiving a source clock and a power down signal and generating clock signals, each of the clock signals corresponding to a respective one of the plurality of processing units.    
     
     
         8 . The signal processing system as recited in  claim 7 , wherein the internal clock signal generator unit includes: 
 a first multiplexor for selectively outputting one of a DC level and the source clock in response to the power down signal;    a branch for branching the output of the first multiplexor into a predetermined number of branches; and    second, third and fourth multiplexors, each for selecting respective ones of the clock signals from the branch and the DC level in response to the power state of a corresponding one of the bit stream processing unit, the digital signal processing unit and to post processing unit, each of the second, third and fourth multiplexors outputting, a selected signal to a respective one of the bit stream processing, digital signal processing and post processing units to output the selected signal to the corresponding processing unit.    
     
     
         9 . The system as recited in  claim 8 , wherein the internal clock signal generator unit includes a logic device for AND operating the outputs of the plurality of multiplexors to drive a memory device.