US2004198039A1PendingUtilityA1

Method and arrangement for contacting terminals

Assignee: INFINEON TECHNOLOGIES AGPriority: Feb 10, 2003Filed: Feb 10, 2004Published: Oct 7, 2004
Est. expiryFeb 10, 2023(expired)· nominal 20-yr term from priority
H10W 20/081H10W 20/40
35
PatentIndex Score
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Claims

Abstract

In a method of contacting terminals, a substrate having a first terminal and a second terminal is provided, a terminal surface of the first terminal being located at a shorter distance from a substrate surface than a surface of the second terminal. A first insulating layer, in which a contact via is formed for exposing the terminal surface of the first terminal, is formed on the substrate surface. The contact via is filled with a conductive material, and a second insulating layer is formed on the first insulating layer and on the contact via filled with the conductive material. Using an etching mask, a first recess for exposing the conductive material filling the contact via, and a second recess are etched through the second and first insulating layers for exposing the second terminal surface. A conductive material for producing first and second contact terminals is introduced into the first and second recesses. This is to achieve that the second terminal is contacted in the production of the second contact terminal.

Claims

exact text as granted — not AI-modified
1 . A method of contacting terminals, the method comprising; 
 providing a substrate having a substrate surface, the substrate comprising a first terminal having a first terminal surface, and a second terminal having a second terminal surface, wherein a distance between the first terminal surface and the substrate surface is smaller than a distance between the second terminal surface and the substrate surface;    forming a first insulating layer on the substrate surface and on the first and second terminal surfaces;    forming a contact via in the first insulating layer for exposing the first terminal surface;    filling the contact via with a conductive material;    forming a second insulating layer on the first insulating layer and on the contact via filled with the conductive material;    forming a etching mask on the second insulating layer, the etching mask specifying an area for a first contact terminal and an area for a second terminal;    etching a first recess through the second insulating layer for exposing the conductive material filling the contact via, and etching a second recess through the second and first insulating layers for exposing the second terminal surface using the etching mask;    introducing a conductive material into the first recess and into the second recess for producing the first and second contact terminals.    
     
     
         2 . The method as claimed in  claim 1 , wherein the first terminal comprises one of a base terminal and a collector terminal, and the second terminal comprises an emitter terminal, arranged on a stack, of a bipolar transistor.  
     
     
         3 . The method as claimed in  claim 1 , wherein the first terminal comprises one of a source and a drain terminal, and the second terminal is comprises a gate terminal of a field-effect transistor.  
     
     
         4 . The method as claimed in  claim 1 , wherein the first terminal is selected from the group of a base terminal of a bipolar transistor, a collector terminal of a bipolar transistor, a gate terminal of a field effect transistor, a source terminal of a field effect transistor and a drain terminal of a field-effect transistor.  
     
     
         5 . The method as claimed in  claim 1 , wherein introducing the conductive material further comprises introducing metal into at least one of the first recess and the second recess.  
     
     
         6 . The method as claimed in  claim 1 , wherein the filling step includes filling the contact via with tungsten.  
     
     
         7 . The method as claimed in  claim 1 , wherein introducing the conductive material includes introducing copper into the first and second recesses.  
     
     
         8 . The method as claimed in  claim 1 , further including the step of forming a wire plane comprising the first contact terminal and the second contact terminal.  
     
     
         9 . The method as claimed in  claim 1 , wherein the step of forming the contact via includes etching the contact via.  
     
     
         10 . The method as claimed in  claim 1 , wherein the etching step includes etching the first recess and the second recess in one pass.  
     
     
         11 . The method as claimed in  claim 1 , wherein introducing the conductive material further comprises introducing the conductive material into the first and second recesses in one pass.  
     
     
         12 . An arrangement for contacting terminals of a substrate comprising a substrate surface, a first terminal having a first terminal surface, and a second terminal having a second terminal surface, the first terminal surface being located at a shorter distance from the substrate surface than the second terminal surface, the arrangement comprising: 
 a first insulating layer on the substrate surface, having an insulation-layer surface being located at a longer distance from the substrate surface than the second terminal surface;    a second insulating layer arranged on the first insulting layer;    wherein the first insulating layer has a contact via which extends from the insulation-layer surface to the first terminal surface and is filled with a first conductive material, and wherein the insulating layer has a recess penetrating the former, extending up to the first conductive material, and being filled with a second conductive material; and    wherein a recess extends to the second terminal surface through the first and second insulating layers, and ins filled with a third conductive material.    
     
     
         13 . The arrangement as claimed in  claim 12 , wherein the first terminal is one of a base terminal and a collector terminal, and the second terminal is an emitter terminal, arranged on a stack, of a bipolar transistor.  
     
     
         14 . The arrangement as claimed in  claim 12 , wherein the first terminal is one of a source terminal and a drain terminal, and the second terminal is a gate terminal of a field-effect transistor.  
     
     
         15 . The arrangement as claimed in  claim 12 , wherein the first terminal is formed on the substrate and is selected from the group of a base terminal of a bipolar transistor, a collector terminal of a bipolar transistor, a gate terminal of a field-effect transistor, a source terminal of a field-effect transistor and a drain terminal of a field-effect transistor.  
     
     
         16 . The arrangement as claimed in  claim 12 , wherein at least one of the first conductive material, the second conductive material and the third conductive material comprises metal.  
     
     
         17 . The arrangement as claimed in  claim 12 , wherein the first conductive material is tungsten.  
     
     
         18 . The arrangement as claimed in  claim 12 , wherein at least one of the second and third conductive materials is copper.  
     
     
         19 . The arrangement as claimed in  claim 12 , wherein the second conductive material is conductively connected to the first conductive material and forms a first contact terminal, and wherein the third conductive material is conductively connected to the second terminal and forms a second contact terminal.  
     
     
         20 . The arrangement as claimed in  claim 12 , wherein the first and second contact terminals form a wiring plane.

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