Semiconductor device having a metal silicide layer and method for manufacturing the same

Abstract

The present invention provides a semiconductor device having a metal silicide layer and a method for forming the metal silicide layer, the semiconductor device having a metal silicide-semiconductor contact structure, wherein the semiconductor device includes a substrate, an insulation layer with an opening, in which a metal silicide layer is formed using a native metal silicide with a first phase and a second phase, upon which a conductive layer is formed. The second phase has a first stoichiometrical composition ratio different from a second stoichiometrical composition ratio of the first phase. A reaction between the metal silicide layer of the first phase and the silicon results in the metal silicide layer of the second phase having high phase stability and low resistance.

1 . A semiconductor device having a metal silicide contact structure, comprising: 
 a substrate;    an insulation layer having an opening formed on the substrate;    a metal silicide layer formed in the opening of the insulation layer; and    a conductive layer formed on the metal silicide layer,    wherein the metal silicide layer is formed between the substrate and the conductive layer and the metal silicide layer has a thickness of less than about 100 Å.    
     
     
         2 . A semiconductor device having a metal silicide contact structure as claimed in  claim 1 , wherein the conductive layer is a semiconductor layer.  
     
     
         3 . A semiconductor device having a metal silicide contact structure as claimed in  claim 1 , wherein the metal silicide layer is formed using a native metal silicide having a first phase and a second phase, the second phase having a first stoichiometrical composition ratio that is different from a second stoichiometrical composition ratio of the first phase.  
     
     
         4 . A semiconductor device having a metal silicide contact structure as claimed in  claim 1 , wherein the substrate is comprised of a material selected from the group consisting of silicon, silicon germanium, silicon-on-insulator (SOI), and silicon-germanium-on-insulator (SGOI).  
     
     
         5 . A semiconductor device having a metal silicide contact structure as claimed in  claim 1 , further comprising a silicon layer or a silicon germanium layer in a form of a crystalline phase or an amorphous phase formed on the substrate.  
     
     
         6 . A semiconductor device having a metal silicide contact structure as claimed in  claim 1 , wherein the conductive layer comprises a silicon layer or a silicon germanium layer in a form of a crystalline phase or an amorphous phase.  
     
     
         7 . A semiconductor device having a metal suicide contact structure as claimed in  claim 1 , wherein the conductive layer is doped polycrystalline silicon.  
     
     
         8 . A semiconductor device having al metal silicide contact structure as claimed in  claim 1 , wherein the metal silicide layer has a resistance between about 3 to 20 Ω/□.  
     
     
         9 . A semiconductor device having a metal silicide contact structure as claimed in  claim 1 , further comprising a gate oxide film formed on the substrate.  
     
     
         10 . A semiconductor device having a metal silicide contact structure as claimed in  claim 9 , further comprising a gate stack formed on the gate oxide film.  
     
     
         11 . A semiconductor device having a metal silicide contact structure as claimed in  claim 10 , further comprising gate sidewall spacers formed on the sides of the gate stack.  
     
     
         12 . A semiconductor device having a metal silicide contact structure as claimed in  claim 9 , further comprising a source/drain area formed on the substrate exposed by the opening in the insulation layer.  
     
     
         13 . A semiconductor device having a metal silicide contact structure as claimed in  claim 1 , further comprising: 
 field oxide films formed on the substrate; and    a pad layer formed between the field oxide films and below the metal silicide layer.    
     
     
         14 . A semiconductor device having a metal silicide contact structure as claimed in  claim 13 , and further comprising: 
 a second insulation layer formed above the field oxide films and the pad layer;    a bit line stack formed on the second insulation layer; and    a third insulation layer formed on the bit line stack and the second insulation layer.    
     
     
         15 . A semiconductor device having a metal silicide contact structure as claimed in  claim 1 , wherein the conductive layer is titanium nitride (TiN).  
     
     
         16 . A semiconductor device having a metal silicide contact structure as claimed in  claim 1 , wherein the conductive layer is a metallic material.  
     
     
         17 . A semiconductor device having a metal silicide contact structure as claimed in  claim 15 , further comprising a metal layer formed on the conductive layer.  
     
     
         18 . A semiconductor device having a metal silicide contact structure, comprising: 
 a substrate;    a gate oxide film formed on the substrate;    a gate stack formed on the gate oxide film;    a metal silicide layer formed on the substrate and the gate stack; and    a capping layer formed above the metal silicide layer, wherein the metal silicide layer has a thickness less than about 100 Å.    
     
     
         19 . A semiconductor device having a metal silicide contact structure as claimed in  claim 18 , further comprising: 
 a source/drain area formed on the substrate;    a lightly-doped source/drain area formed on the substrate between the metal silicide layer formed on the substrate and the gate oxide film; and    gate sidewall spacers formed on sides of the gate stack.    
     
     
         20 - 43 . (Cancelled)