Semiconductor integrated circuit device and manufacturing method thereof

Abstract

A silicon oxide film on which a capacitor of a semiconductor integrated circuit device is formed is formed by the plasma CVD method at a temperature of 450° C. to 700° C. In this semiconductor integrated circuit device, a memory cell formed of a MISFET for data transfer and a capacitor is formed in a memory cell forming area, and an n channel MISFET and a p channel MISFET constituting a logic circuit is formed in a logic circuit forming area. As a result, the amount of degassing from the silicon oxide film can be reduced. Therefore, the growth of silicon grains on a surface of the silicon film constituting a lower electrode of the capacitor is not hindered by the degassing, and it becomes possible to increase the capacitance. Also, the step of a heat treatment for removing the moisture and the like after forming the silicon oxide film can be omitted, and it becomes possible to prevent the deterioration of the property of the MISFET.

1 - 19 . (cancelled)  
     
     
         20 . A semiconductor integrated circuit device, comprising: 
 (a) a MISFET formed on a main surface of a semiconductor substrate and    (b) a capacitor connected in series with said MISFET, wherein said capacitor comprises:    (b1) a lower electrode made of a silicon film, which is formed at a concave portion in a lamination layer of a first insulating film formed above said MISFET and a second insulating film formed on said first insulating film and having smaller impurity content than said first insulating film;    (b2) a capacitor insulating film formed on said lower electrode; and    (b3) an upper electrode formed of a conductive film formed on said capacitor insulating film.    
     
     
         21 . The semiconductor integrated circuit device, according to  claim 20 , wherein said capacitor is connected with said MISFET by a series of plugs which are comprised of a first plug contacting said semiconductor substrate and a second plug contacting said capacitor, wherein said first plug has smaller diameter than said second plug.  
     
     
         22 . The semiconductor integrated circuit device, according to  claim 20 , wherein a bit line is connected with said MISFET via plugs which are comprised of a first plug contacting said semiconductor substrate and a second plug contacting said bit line, wherein said first plug has larger diameter than said second plug.  
     
     
         23 . The semiconductor integrated circuit device, according to  claim 20 , wherein a plug formed in a peripheral circuit is connected with said semiconductor substrate via a silicide layer formed on said semiconductor substrate.  
     
     
         24 . The semiconductor integrated circuit device, according to  claim 20 , wherein an upper surface of said lower electrode is below an upper surface of said second insulating film.  
     
     
         25 . A semiconductor integrated circuit device, comprising: 
 (a) a MISFET formed on a main surface of a semiconductor substrate; and    (b) a capacitor connected in series with said MISFET, wherein said capacitor comprises:    (b1) a lower electrode made of a silicon film, which is formed at a concave portion in a lamination layer of a first insulating film formed above said MISFET and a second insulating film which is thinner than said first insulating film and formed on said first insulating film;    (b2) a capacitor insulating film formed on said lower electrode; and    (b3) an upper electrode formed of a conductive film formed on said capacitor insulating film.    
     
     
         26 . The semiconductor integrated circuit device, according to  claim 25 , wherein said second insulating film has a smaller impurity content than said first insulating film.  
     
     
         27 . The semiconductor integrated circuit device, according to  claim 25 , wherein said capacitor is connected with said MISFET by a series of plugs which are comprised of a first plug contacting said semiconductor substrate and a second plug contacting said capacitor, wherein said first plug has smaller diameter than said second plug.  
     
     
         28 . The semiconductor integrated circuit device, according to  claim 25 , wherein a bit line is connected with said MISFET via plugs which are comprised of a first plug contacting said semiconductor substrate and a second plug contacting said bit line, wherein said first plug has larger diameter than said second plug.  
     
     
         29 . The semiconductor integrated circuit device, according to  claim 25 , wherein a plug formed in a peripheral circuit is connected with said semiconductor substrate via a silicide layer formed on said semiconductor substrate.  
     
     
         30 . The semiconductor integrated circuit device, according to  claim 25 , wherein an upper surface of said lower electrode is below an upper surface of said second insulating film.