US2004192052A1PendingUtilityA1

Viscous protective overlayers for planarization of integrated circuits

Priority: Jan 23, 2001Filed: Nov 17, 2003Published: Sep 30, 2004
Est. expiryJan 23, 2021(expired)· nominal 20-yr term from priority
H10P 50/667H10W 20/4424H10W 20/425H10W 20/062H10P 95/04H10P 50/00Y10S977/788Y10S977/712C23F 3/06
39
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

The present invention relates to the planarization of surfaces as typically encountered in the fabrication of integrated circuits, particularly copper conductors and Ta/TaN barrier layers encountered in damascene and dual damascene interconnects. The present invention describes planarization methods for Cu/Ta/TaN interconnects, typically making use of a viscous overlayer tending to dwell in regions of lower surface topography, protecting said lower regions from etching by a combination of chemical and mechanical effects. In some embodiments, the viscous overlayer contains species that hinder removal of copper from regions of the surface in contact with the viscous layer. Such species may be a substantially saturated solution of copper ions among other additives, thereby hindering the dissolution of interconnect copper into the protective overlayer. In some embodiments of the present invention, the viscous overlayer may be added prior to the introduction of etchant to the wafer surface, or both etchant and viscous overlayer may be introduced substantially simultaneously, typically as the wafer is spun during planarization.

Claims

exact text as granted — not AI-modified
We claim:  
     
         1 ) A method of planarizing a metal surface in the fabrication of integrated circuit interconnects comprising: 
 a) introducing a protecting fluid onto said metal surface; and,    b) dispersing said protecting fluid across said metal surface; and,    c) introducing an etching solution onto said metal surface, whereby the viscosity of said protecting fluid exceeds that of said etching solution thereby hindering etching of said surface in regions of said surface occupied by said protecting layer; and,    d) etching said metal surface to planarity.    
     
     
         2 ) A method as in  claim 1  wherein said protecting fluid lacks oxidants capable of etching said metal surface.  
     
     
         3 ) A method as in  claim 2  wherein said introduction of said protecting fluid onto said metal surface is in sufficient quantity to provide preferential protection to depressed regions of said metal surface.  
     
     
         4 ) A method as in  claim 3  wherein said protecting fluid contains dissolved therein a saturating amount of ion of the metal comprising said metal surface.  
     
     
         5 ) A method as in  claim 4  wherein said metal is copper.  
     
     
         6 ) A method as in  claim 5  wherein said protecting fluid is phosphoric acid containing a saturating amount of copper ions dissolved therein.  
     
     
         7 ) A method as in claim I wherein said protecting fluid and said etching solution are introduced onto said metal surface substantially simultaneously.  
     
     
         8 ) A precursor for an integrated circuit comprising: 
 a) insulating dielectric layer; and,    b) barrier layer; and,    c) conductor; and,    d) protecting fluid; and,    e) etching fluid whereby the viscosity of said protecting fluid exceeds the viscosity of said etching fluid.    
     
     
         9 ) The precursor of  claim 8  wherein said barrier layer is tantalum/tantalum nitride.  
     
     
         10 ) The precursor of  claim 8  wherein said conductor is copper.

Join the waitlist — get patent alerts

Track US2004192052A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.