Semiconductor device with fully self-aligned local interconnects, and method for fabricating the device

Abstract

A semiconductor device and a method for making it involve the semiconductor device ( 10, 110, 210, 310 ) having a substrate ( 11, 311 ) with spaced source and drain regions ( 13 - 14, 316 - 318, 321 - 323 ). A gate section ( 21 ) projects upwardly from between an adjacent pair of these regions, into an insulating layer ( 46, 363 ). In order to create local interconnects to the source and drain regions through the insulating layer, a patterned etch is carried out using an etch region ( 51 ), which extends over one of the gate sections from a location above one of the regions to a location above another of the regions. Etching in this etch region produces recesses ( 56 - 57 ) on opposite sides of and immediately adjacent the gate section. A conductive layer ( 61, 120 ) is deposited to fill the recesses, and then is planarized back to the upper ends of the gate sections. The portion of the conductive material remaining in each recess is self-aligned to be immediately adjacent at least one gate section, and serves as a local interconnect for a respective source or drain region.

1 - 15  (cancelled)  
     
     
         16 . An apparatus comprising a semiconductor device which includes: 
 a semiconductor substrate having spaced first and second sections which are respectively a source region and a drain region and which have respective upwardly facing first and second surface portions thereon;    a third section projecting upwardly beyond each of said first and second surface portions from a location therebetween, said third section being a gate section which includes a gate dielectric layer, a gate electrode over said gate dielectric layer, and insulator sidewalls on opposite sides of said gate dielectric layer and said gate electrode, said gate electrode having on an upper side thereof a third surface portion;    an insulating layer which has portions disposed over said first and second surface portions, said third section extending into said insulating layer, and said insulating layer having first and second recess portions which respectively extend downwardly through said insulating layer toward said first and second surface portions on opposite sides of said third section, each said recess portion being immediately adjacent a respective side of said third section;    a first portion of conductive material disposed in said first recess portion and having on an upper side thereof a fourth surface portion; and    a second portion of conductive material disposed in said second recess portion and having on an upper side thereof a fifth surface portion, said third, fourth and fifth surface portions being substantially coplanar with each other and with an upper surface of said insulating layer.    
     
     
         17 . An apparatus according to  claim 16 , including a silicide formed at each of said first, second and third surface portions.  
     
     
         18 . An apparatus according to  claim 16 , wherein said insulator sidewalls each project upwardly beyond said third surface portion on said gate electrode.  
     
     
         19 . An apparatus according to  claim 16 , including a second insulating layer which is provided over said first insulating layer, and which has an opening therein that extends through said second insulating layer and exposes at least one of said third, fourth and fifth surface portions; and including a portion of a conductive material disposed in said opening.