Method of and apparatus for manufacturing a semiconductor device using a polysilicon hard mask
Abstract
A method and apparatus for use in manufacturing a semiconductor device strips a polysilicon hard mask without damaging the layer left exposed by openings formed by using the polysilicon hard mask as an etching mask. The method includes forming a polysilicon hard mask in a pattern on a first layer to expose a portion of the first layer, dry etching the exposed portion of the first layer using the polysilicon hard mask as an etching mask to form an opening in the first layer, and thereafter removing the polysilicon hard mask by supplying an etching gas onto the polysilicon hard mask in a direction parallel to the major surface of the semiconductor substrate. The processing apparatus includes a reaction chamber including a spin chuck which supports the semiconductor substrate for rotation, a gas supply unit for supplying a process gas to the reaction chamber, a gas injection unit for injecting the process gas supplied by the gas supply unit into the reaction chamber in a direction parallel to the major surface of the semiconductor substrate, and an exhaust unit for exhausting gases from the reaction chamber.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . An etching process for use in manufacturing a semiconductor device, comprising:
forming a first layer on a semiconductor substrate; forming a polysilicon hard mask on the first layer, the polysilicon hard mask having a pattern such that a portion of the first layer is exposed; dry etching the exposed portion of the first layer using the polysilicon hard mask as an etching mask to form an opening in the first layer; and supplying an etching gas onto the polysilicon hard mask in a direction substantially parallel to the major upper surface of the semiconductor substrate to thereby dry etch the polysilicon hard mask.
2 . The process of claim 1 , and further comprising forming a conductive layer on the semiconductor substrate, and wherein the forming of the first layer comprises forming a dielectric film on the conductive layer.
3 . The process of claim 1 , wherein the dry etching of the first layer forms an opening which exposes the surface of the semiconductor substrate, and further comprising subsequently etching the exposed portion of the semiconductor substrate to form a trench in the semiconductor substrate.
4 . The process of claim 1 , wherein the supplying of an etching gas comprises supplying an etching gas which reacts with the silicon of the polysilicon hard mask.
5 . The process of claim 1 , wherein the supplying of an etching gas comprises supplying a fluorine-containing compound.
6 . The process of claim 5 , wherein the etching gas comprises at least one halogen fluoride selected from the group consisting of CIF, CIF 3 , BrF, BrF 3 , BrF 5 , IF, IF 3 and IF 5 .
7 . The process of claim 5 , wherein the etching gas comprises XeF 2 .
8 . The process of claim 1 , wherein the dry etching of the polysilicon hard mask comprises supplying the etching gas along with a carrier gas.
9 . The process of claim 8 , wherein the carrier gas is one of nitrogen and argon.
10 . The process of claim 1 , wherein the dry etching of the polysilicon hard mask comprises rotating the semiconductor substrate while the polysilicon hard mask is exposed to the etching gas.
11 . The process of claim 1 , wherein the dry etching of the polysilicon hard mask comprises supplying the etching gas in a series of pulses of a predetermined period.
12 . The process of claim 11 , wherein the dry etching of the polysilicon hard mask is carried out at a pressure of at most several tens of mTorr.
13 . The process of claim 11 , wherein the dry etching of the polysilicon hard mask is carried out at room temperature.
14 . The process of claim 11 , wherein the dry etching of the polysilicon hard mask comprises rotating the semiconductor substrate while the polysilicon hard mask is exposed to the etching gas.
15 . An apparatus for use in manufacturing a semiconductor device, comprising:
a reaction chamber comprising a casing, and a spin chuck disposed within said casing, said spin chuck being configured to support a semiconductor substrate and being rotatable, whereby a semiconductor substrate supported thereon can be rotated; a gas supply unit connected to said reaction chamber, said gas supply unit supplying the reaction chamber with a process gas for removing unnecessary material from a semiconductor substrate mounted to the spin chuck in the reaction chamber; a gas injection unit connecting said gas supply unit to said reaction chamber, said gas injection unit having at least one gas injection opening, each said at least one gas injection opening being oriented such that the gas injection unit injects the process gas, supplied by the gas supply unit, into the reaction chamber in a horizontal direction substantially parallel to the major upper surface of a semiconductor substrate mounted to the spin chuck in the reaction chamber, and an exhaust unit connected to said reaction chamber so as to exhaust gases from the reaction chamber.
16 . The apparatus of claim 15 , wherein said gas supply unit comprises a source of a fluorine-containing gaseous compound.
17 . The apparatus of claim 16 , wherein the compound is a gas selected from the group consisting of CIF, CIF 3 , BrF, BrF 3 , BrF 5 , IF, IF 3 , IF 5 and XeF 2 .
18 . The apparatus of claim 16 , wherein said gas supply unit further comprises a source of a carrier gas.
19 . The apparatus of claim 15 , wherein said gas injection unit is disposed on an inner side wall of said casing of the reaction chamber, and comprises a shower head having a plurality of gas injection openings through which the process gas flows into the reaction chamber in a horizontal direction above said spin chuck.
20 . The apparatus of claim 15 , and further comprising a puff valve connected in-line between said gas supply unit and said reaction chamber, said puff valve being operative to supply the process gas flowing from the gas supply unit into the reaction chamber as a series of pulses of a predetermined period.Join the waitlist — get patent alerts
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