Input/output architecture for integrated circuits with efficeint positioning of integrated circuit elements

Abstract

A described embodiment of the present invention includes an integrated circuit having a plurality of I/O modules. The I/O modules include a bond pad formed on a substrate. The I/O modules also include an electrostatic discharge device formed in the substrate. The electrostatic discharge device is at least partially formed beneath the bond pad. The I/O module also includes an I/O buffer formed in the substrate. The I/O buffer is connected to the bond pad. The I/O buffer provides communication between the bond pad and circuitry formed in the substrate. The circuitry is positioned substantially adjacent to both the electrostatic discharge device and the I/O buffer.

Having thus described my invention, what I claim as new and desire to secure by Letters Patent is set forth in the following claims.  
     
         1 . An integrated circuit having a plurality of I/O modules comprising: 
 a bond pad formed on a substrate;    an electrostatic discharge device formed in the substrate, the electrostatic discharge device being at least partially formed beneath the bond pad;    an I/O buffer formed in the substrate and connected to the bond pad, the I/O buffer providing communication between the bond pad and circuitry formed in the substrate, wherein the circuitry is positioned substantially adjacent to both the electrostatic discharge device and the I/O buffer.    
     
     
         2 . The integrated circuit of  claim 1  wherein the substrate is a silicon substrate.  
     
     
         3 . The integrated circuit of  claim 1  wherein the I/O buffer is an output buffer.  
     
     
         4 . The integrated circuit of  claim 1  wherein the I/O buffer is an input buffer.  
     
     
         5 . The integrated circuit of  claim 1  wherein the I/O buffer is a complementary output buffer.  
     
     
         6 . The integrated circuit of  claim 1  wherein the circuitry is CMOS circuitry.  
     
     
         7 . The integrated circuit of  claim 1  wherein the circuitry is BiCMOS circuitry.  
     
     
         8 . The integrated circuit of  claim 1  wherein the circuitry is an application specific integrated circuit.  
     
     
         9 . The integrated circuit of  claim 1  wherein the circuitry is digital signal processor.  
     
     
         10 . The integrated circuit of  claim 1  wherein the entire surface of the substrate beneath the bond pad is occupied by the electrostatic discharge device.  
     
     
         11 . An integrated circuit comprising: 
 a functional core formed on a substrate, the functional core being positioned centrally on the substrate; and    an I/O region positioned at the periphery of the functional core, the I/O region including a plurality of I/O modules, the I/O modules including: 
 a bond pad formed on a substrate;  
 an electrostatic discharge device; and  
 an I/O buffer wherein the I/O buffer is not positioned between the bond pad and the functional core.  
   
     
     
         12 . The integrated circuit of  claim 11  wherein the substrate is a silicon substrate.  
     
     
         13 . The integrated circuit of  claim 11  wherein the I/O buffer is an output buffer.  
     
     
         14 . The integrated circuit of  claim 11  wherein the I/O buffer is an input buffer.  
     
     
         15 . The integrated circuit of  claim 11  wherein the I/O buffer is a complementary output buffer.  
     
     
         16 . The integrated circuit of  claim 11  wherein the functional core is CMOS circuitry.  
     
     
         17 . The integrated circuit of  claim 11  wherein the functional core is BiCMOS circuitry.  
     
     
         18 . The integrated circuit of  claim 11  wherein the functional core is an application specific integrated circuit.  
     
     
         19 . The integrated circuit of  claim 11  wherein the functional core is digital signal processor.  
     
     
         20 . The integrated circuit of  claim 11  wherein the entire surface of the substrate beneath the bond pad is occupied by the electrostatic discharge device.  
     
     
         21 . An integrated circuit comprising: 
 a functional core formed on a substrate, the functional core including a plurality of integrated circuit elements and being positioned centrally on the substrate; and    an I/O region positioned at the periphery of the functional core, the I/O region including a plurality of I/O modules, the I/O modules including: 
 a bond pad formed on a substrate, the bond pad including a conductive surface for providing electrical connection to external devices;  
 an electrostatic discharge device formed beneath the bond pad; and  
 a CMOS I/O buffer wherein the I/O buffer is not positioned between the bond pad and the functional core.  
   
     
     
         22 . A method for forming an integrated circuit having a plurality of I/O modules comprising: 
 forming a bond pad formed on a substrate;    forming an electrostatic discharge device formed in the substrate, the electrostatic discharge device being at least partially formed beneath the bond pad; and    forming an I/O buffer formed in the substrate and connected to the bond pad, the I/O buffer providing communication between the bond pad and circuitry formed in the substrate, wherein the circuitry is positioned substantially adjacent to both the electrostatic discharge device and the I/O buffer.    
     
     
         23 . The method of  claim 22  wherein the substrate is a silicon substrate.  
     
     
         24 . The method of  claim 22  wherein the I/O buffer is an output buffer.  
     
     
         25 . The method of  claim 22  wherein the I/O buffer is an input buffer.  
     
     
         26 . The method of  claim 22  wherein the I/O buffer is a complementary output buffer.  
     
     
         27 . The method of  claim 22  wherein the circuitry is CMOS circuitry.  
     
     
         28 . The method of  claim 22  wherein the circuitry is BiCMOS circuitry.  
     
     
         29 . The method of  claim 22  wherein the circuitry is an application specific integrated circuit.  
     
     
         30 . The method of  claim 22  wherein the circuitry is digital signal processor.  
     
     
         31 . The method of  claim 22  wherein the entire surface of the substrate beneath the bond pad is occupied by the electrostatic discharge device.  
     
     
         32 . A method for forming an integrated circuit comprising: 
 providing a functional core formed on a substrate, the functional core being positioned centrally on the substrate; and    in an I/O region positioned at the periphery of the functional core, forming a plurality of I/O modules, the steps for forming the I/O modules including: 
 forming a bond pad formed on a substrate;  
 forming an electrostatic discharge device; and  
 forming an I/O buffer wherein the I/O buffer is not positioned between the bond pad and the functional core.  
   
     
     
         33 . The method of  claim 32  wherein the substrate is a silicon substrate.  
     
     
         34 . The method of  claim 32  wherein the I/O buffer is an output buffer.  
     
     
         35 . The method of  claim 32  wherein the I/O buffer is an input buffer.  
     
     
         36 . The method of  claim 32  wherein the I/O buffer is a complementary output buffer.  
     
     
         37 . The method of  claim 32  wherein the functional core is CMOS circuitry.  
     
     
         38 . The method of  claim 32  wherein the functional core is BiCMOS circuitry.  
     
     
         39 . The method of  claim 32  wherein the functional core is an application specific integrated circuit.  
     
     
         40 . The method of  claim 32  wherein the functional core is digital signal processor.  
     
     
         41 . The method of  claim 32  wherein the entire surface of the substrate beneath the bond pad is occupied by the electrostatic discharge device.