Out-of-order processor executing speculative-load instructions

Abstract

In addition to speculatively executing normal (non-speculative) load instructions in advance of their program order, an out-of-order processor executes the speculative (advanced) load instructions originally compiled for in-order processors. Both the speculative-load instructions and the corresponding check instructions can be executed out-of-order. The speculative-load instructions are treated like normal-load instructions while in the instruction queue. When a speculative-load instruction is retired from the instruction queue, it is transferred to a speculative load instruction manager. Execution of the corresponding check instruction can then check the validity of the speculative-load instruction.

What is claimed is:  
     
         1 . A data processor for executing instructions: 
 an instruction handler for holding a series of said instructions for execution;    an instruction manager for determining an order for executing the instructions in said instruction handler, said instruction manager providing for out-of-order execution of said instructions; and    an execution unit for executing said instructions, said execution unit providing for execution of a speculative-load instruction and an associated subsequent check instruction that determines whether or not said speculative-load instruction has failed.    
     
     
         2 . A data processor as recited in  claim 1  further comprising a speculative-load manager, said speculative-load manager storing information associated with a said speculative-load instruction between the time it is retired from said instruction handler and the execution of said check instruction.  
     
     
         3 . A data processor as recited in  claim 2  wherein said execution unit, when executing said check instruction 
 before said speculative-load instruction has been retired from said instruction handler, determines whether or not said speculative-load instruction has failed using information stored in said instruction handler, and  
 after said speculative-load instruction has been retired from said instruction handler, determines whether or not said speculative-load instruction has failed using information stored by said speculative-load manager.  
 
     
     
         4 . A data processor as recited in  claim 1  wherein said execution unit executes a check instruction only after the corresponding speculative-load instruction has retired from said instruction handler.  
     
     
         5 . A data processor as recited in  claim 1  wherein said execution unit sometimes executes a check instruction while the corresponding speculative-load instruction is in said instruction handler.  
     
     
         6 . A data processor as recited in  claim 2  wherein said instruction manager provides for out-of-order execution of said speculative-load instruction.  
     
     
         7 . A data processor as recited in  claim 1  wherein said instruction manager provides for out-of-order execution of said check instruction.  
     
     
         8 . A method of executing a computer program of instructions, each of said instructions having an associated program order, defining an instruction order, said instructions including an advanced-load instruction and an associated check instruction, said method comprising: 
 executing said advanced-load instruction in advance of its program order; and    subsequently executing said check instruction.    
     
     
         9 . A method as recited in  claim 8  wherein said step of executing said advanced-load instruction involves transferring data into a processor register.  
     
     
         10 . A data processor comprising: 
 an instruction handler for receiving program instructions having a program order; said program instructions including an advanced load instruction and a corresponding check instruction; and    an execution unit for executing said advanced-load instruction in advance of its program order.    
     
     
         11 . A data processor as recited in  claim 10  further comprising a data register to which data is written when said execution unit executes said advanced-load instruction.